STK5F4U3C2D-E

No.A2299-7/15

Input / Output Timing Chart

Notes:

*1 : Diagram shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for

switching delay externally.

*2 : When VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will

resume immediately.

*3 : When the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The

outputs return to normal operation immediately after the upper side gate voltage rises.

*4 : When VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2ms (typ) after over current

condition is removed.

Fig.7

ON

OFF

HIN1,2,3

LIN1,2,3

ITRIP terminal

Voltage

Upper

U, V, W

Lower

U ,V, W

VB1,2,3

*1

*1

OFF

ON

*2

*3

VBS undervoltage protection reset signal

VDD undervoltage protection reset voltage

VIT≥0.54V

VIT<0.44V

Automatically reset after protection

(typ.2ms)

*4

VDD

VBS undervoltage protection reset voltage

FAULT terminal

Voltage

(at pulled-up)