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STK5F1U3E3D-E Datasheet(PDF) 7 Page - ON Semiconductor |
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STK5F1U3E3D-E Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 16 page ![]() STK5F1U3E3D-E www.onsemi.com 7 Logic Timing Chart Fig. 8 Notes *1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be added externally. *2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the operation will resume immediately. *3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gat voltage rises. *4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 1.3 to 2.5ms after the over current condition is removed. ON OFF HIN1,2,3 LIN1,2,3 ITRIP-terminal (BUS line) Current Upper U, V, W Lower U ,V, W VB1,2,3 *1 *1 OFF ON *2 *3 VBS undervoltage protection reset signal VDD undervoltage protection reset voltage -------------------------------------------------------ISD operation current level------------------------------------------------------- Automatically reset after protection (1.3ms to 2.5ms) *4 VDD VBS undervoltage protection reset voltage FAULT terminal Voltage (at pulled-up) |
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