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BQ76PL455A Datasheet(PDF) 4 Page - Texas Instruments |
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BQ76PL455A Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 125 page  4 bq76PL455A SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) NAME TYPE(1) DESCRIPTION PIN NO. CGND 48 P Communication ground(2). Connect to ground plane. CHM 33 P Charge pump flying capacitor connection. Connect a 22-nF ceramic capacitor(3) between this pin and CHP. CHP 32 P Charge pump flying capacitor connection. Connect a 22-nF ceramic capacitor(3) between this pin and CHM. COMMH– 54 DIO Inverting, high-side differential connection to the COMML– pin of the higher adjacent module in a daisy chain. Leave this pin unconnected if not used. COMMH+ 55 DIO Non-inverting, high-side differential connection to the COMML+ pin of the higher adjacent module in a daisy chain. Leave this pin unconnected if not used. COMML– 53 DIO Inverting, low-side differential connection to the COMMH– pin of the lower adjacent module in a daisy chain. Leave this pin unconnected if not used. COMML+ 52 DIO Non-inverting, low-side differential connection to the COMMH+ pin of the lower adjacent module in a daisy chain. Leave this pin unconnected if not used. DGND1 30 P Digital Ground(2). Connect to ground plane. DGND2 35 P Digital Ground(2). Connect to ground plane. DGND3 37 P Digital Ground(2). Connect to ground plane. EQ1 28 DO Cell Equalization control output used to drive an external N-FET balancing cell 1. May leave this pin unconnected if not used. EQ2 26 DO Cell Equalization control output used to drive an external N-FET balancing cell 2. May leave this pin unconnected if not used. EQ3 24 DO Cell Equalization control output used to drive an external N-FET balancing cell 3. May leave this pin unconnected if not used. EQ4 22 DO Cell Equalization control output used to drive an external N-FET balancing cell 4. May leave this pin unconnected if not used. EQ5 20 DO Cell Equalization control output used to drive an external N-FET balancing cell 5. May leave this pin unconnected if not used. EQ6 18 DO Cell Equalization control output used to drive an external N-FET balancing cell 6. May leave this pin unconnected if not used. EQ7 16 DO Cell Equalization control output used to drive an external N-FET balancing cell 7. May leave this pin unconnected if not used. EQ8 14 DO Cell Equalization control output used to drive an external N-FET balancing cell 8. May leave this pin unconnected if not used. EQ9 12 DO Cell Equalization control output used to drive an external N-FET balancing cell 9. May leave this pin unconnected if not used. EQ10 10 DO Cell Equalization control output used to drive an external N-FET balancing cell 10. May leave this pin unconnected if not used. EQ11 8 DO Cell Equalization control output used to drive an external N-FET balancing cell 11. May leave this pin unconnected if not used. EQ12 6 DO Cell Equalization control output used to drive an external N-FET balancing cell 12. May leave this pin unconnected if not used. EQ13 4 DO Cell Equalization control output used to drive an external N-FET balancing cell 13. May leave this pin unconnected if not used. EQ14 2 DO Cell Equalization control output used to drive an external N-FET balancing cell 14. May leave this pin unconnected if not used. EQ15 80 DO Cell Equalization control output used to drive an external N-FET balancing cell 15. May leave this pin unconnected if not used. EQ16 78 DO Cell Equalization control output used to drive an external N-FET balancing cell 16. May leave this pin unconnected if not used. FAULT_N 40 DO Single-ended active-low fault output. Leave this pin unconnected if not used. FAULTH– 56 DI Inverting, high-side differential connection to the FAULTL– pin of the higher adjacent module in a daisy chain. Leave this pin unconnected if not used. |
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