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ADUM1200 Datasheet(PDF) 8 Page - Analog Devices |
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ADUM1200 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page  ADuM1200/ADuM1201 Rev. B | Page 8 of 20 Parameter Symbol Min Typ Max Unit Test Conditions 25 Mbps (CR Grade Only) VDD1 Supply Current IDD1 (25) 5 V/3 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 5 V/3 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB ≤ VDD1 or VDD2 Logic High Input Threshold VIH 0.7 VDD1, VDD2 V Logic Low Input Threshold VIL 0.3 VDD1, VDD2 V 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages VOAH, VOBH VDD1, VDD2 − 0.1 VDD1, VDD2 V IOx = −20 µA, VIx = VIxH VDD1, VDD2− 0.5 VDD1, VDD2 − 0.2 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 µA, VIx = VIxL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels ADuM120xBR Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 15 55 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing Directional Channels6 tPSKOD 22 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tf CL = 15 pF, CMOS signal levels 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns |
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