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OM25180FDKM Datasheet(PDF) 14 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 14 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend Timers T0 to T2 has a resolution of 20 bits and may be operated at clock frequencies derived from the 13.56 MHz system clock. Several start events can be configured: start now, start on external RF-field on/off and start on Rx (receive)/Tx (transmit) started/ended. The timers allow reload of the counter value. At expiration of the timers, a flag is raised and an IRQ is triggered. The clock may be divided by a prescaler for frequencies of: • 6.78 MHz • 3.39 MHz • 1.70 MHz • 848 kHz • 424 kHz • 212 kHz • 106 kHz • 53 kHz 11.3.2 Interrupt System 11.3.2.1 IRQ PIN The IRQ_ENABLE_REG configures, which of the interrupts are routed to the IRQ pin of the PN5180. All of the interrupts can be enabled and disabled independent from each other. The IRQ on the pin can either be cleared by writing to the IRQ_SET_CLEAR register or by reading the IRQ_STATUS register (EEPROM configuration). If not all enabled IRQ’s are cleared, the IRQ pin remains active. The polarity of the external IRQ signal is configured by EEPROM in IRQ_PIN_CONFIG (01Ah). 11.3.2.2 IRQ_STATUS Register The IRQ_STATUS register contains the status flags. The status flags cannot be disabled. Status Flag can either be cleared by writing to the IRQ_SET_CLEAR register or when the IRQ_STATUS register is read (EEPROM configuration) The PN5180 indicates certain events by setting bits in the register GENERAL_IRQ_STATUS_REG and additionally, if activated, on the pin IRQ. LPCD_IRQ, GENERAL_ERROR_IRQ and HV_ERROR_IRQ are non-maskable interrupts. 11.4 SPI Host Interface The following description of the SPI host interface is valid for the NFC operation mode. The Secure Firmware Download mode uses a different physical host interface handling. Details are described in chapter 12. 11.4.1 Physical Host Interface The interface of the PN5180 to a host microcontroller is based on a SPI interface, extended by signal line BUSY. The maximum SPI speed is 7 Mbps and fixed to CPOL = 0 and CPHA = 0. Only a half-duplex data transfer is supported. There is no chaining |
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