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OM25180FDKM Datasheet(PDF) 13 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 13 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend The clock applied to the PN5180 provides a time basis for the RF encoder and decoder. The stability of the clock frequency, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. Optimum performance is best achieved using the internal oscillator buffer with the recommended circuitry. In card emulation mode, the clock is also required. If an external clock source of 27.12 MHz is used instead of a crystal, the clock signal must be applied to pin CLK1. In this case, special care must be taken with the clock duty cycle and clock jitter (see Table 127). The crystal is a component which is impacting the overall performance of the system. A high-quality component is recommended here. The resistor RD1 reduces the start-up time of the crystal. A short start-up time is especially desired in case the Low-Power card detection is used. The values of these resistors depend on the crystal which is used. 11.3 Timer and Interrupt system 11.3.1 General Purpose Timer The Timers are used to measure certain intervals between certain configurable events of the receiver, transmitter and other RF-events. The timer signals its expiration by raising a flag and the value of the timer may be accessed via the register-set. Three general-purpose timers T0, T1, and T2 running with the PN5180 clock with several start conditions, stop conditions, time resolutions, and maximal timer periods are implemented. For automatic timeout handling during MIFARE Authentication Timer2 is blocked during this operation. In case EMVCo EMD handling is enabled (EMD_CONTROL register (address 0028h), bit EMD_ENABLE) Timer1 is automatically restarted when an EMD event occurs. Fig 5. Connection of crystal aaa-020196 CLK1 CLK2 RD1 RD1 CL1 CL1 crystal PN5180 VSS |
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