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OM25180FDKM Datasheet(PDF) 11 Page - NXP Semiconductors

Part # OM25180FDKM
Description  High-performance multi-protocol full NFC Forum-compliant frontend
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

OM25180FDKM Datasheet(HTML) 11 Page - NXP Semiconductors

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PN5180
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 7 October 2016
240930
11 of 149
NXP Semiconductors
PN5180
High-performance multi-protocol full NFC Forum-compliant frontend
TVDD - Transmitter supply
AVDD - Analog supply input, connected to VDD
DVDD - Digital supply input, connected to VDD
VDD - 1.8 V output, to be connected to AVDD and DVDD
Decoupling capacitors shall be placed as close as possible to the pins of the package.
Any additional filtering/damping of the transmitter supply, e.g. by ferrite beads, might have
an impact on the analog RF signal quality and shall be monitored carefully.
Power-up sequence of the PN5180
First ramp VBAT, PVDD can immediately follow, latest 2 ms after VBAT reaches 1.8 V.
There is no timing dependency on TVDD, only that TVDD shall rise equal or later to
VBAT.
VBAT must be equal or higher than PVDD
TVDD has no other relationship to VBAT or PVDD
After power-up, the PN5180 is indicating the ability to receive command from a host
microcontroller by an IDLE IRQ.
There are configurations in EEPROM, which allow to specify the behavior of the PN5180
after start-up. LPCD (Low-power card detection) and DPC (dynamic power control) are
functionalities which are configurable in EEPROM.
11.2.1.2
Power-down
A hard power-down is enabled with LOW level on pin RESET_N. This low level puts the
internal voltage regulators for the analog and digital core supply as well as the oscillator in
a low-power state. All digital input buffers are separated from the input pads and clamped
Fig 4.
Power-up voltages
aaa-020676
1.8 V
max Δ2ms
PVDD
time
VBAT
voltage


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