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OM25180FDKM Datasheet(PDF) 104 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 104 Page - NXP Semiconductors |
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104 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 104 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend Table 104. EMD_CONTROL register (address 0028h) bit description Bit Symbol Access Value Description Recommended value for EMVCo 2.3.1 0x185 (use Timer1) Recommended value for EMVCo 2.5 0x187 10:31 RFU R 0 Reserved 8:9 EMD_TRANSMISSION_TIMER_ USED R/W 0 Timer used for RF communication. 00 Timer0, 01 Timer1, 10 Timer 2, 11 RFU 7 up to firmware version 2.4 EMD_MISSING_CRC_IS_PROT OCOL_ERROR_TYPE_B R/W 0 Missing CRC treated as protocol error in case of Type B based communication. Only applicable for EMVCo 2.3.1. from firmware 2.5 onwards R/W 0 RFU 6 up to firmware version 2.4 EMD_MISSING_CRC_IS_PROT OCOL_ERROR_TYPE_A R/W 0 Missing CRC treated as protocol error in case of Type A based communication. Only applicable for EMVCo 2.3.1. from firmware 2.5 onwards R/W 0 RFU 2:5 EMD_NOISE_BYTES_THRESH OLD R/W 0 Defines the threshold under which transmission errors are treated as noise. Note: CRC bytes are NOT included/counted! 1 EMD_TRANSMISSION_ERROR _ABOVE_NOISE_THRESHOLD _IS_NO_EMD R/W 0 Transmission errors with received byte length >= EMD_NOISE_BYTES_THRESHOLD is never treated as EMD (EMVCo 2.5 standard). All transmission with number of received bytes < 4 bytes are treated as EMD noise, (ignored). For transmission errors >= 4 bytes the host is notified. 0 EMD_ENABLE R/W 0 Enable EMD handling Table 105. ANT_CONTROL register (address 0029h) bit description Bit Symbol Access Value Description 8:31 RFU R 0 Reserved 7 ANT_INVERT_ON_TXACTIVE R/W 0 If set to 1, the ANT short interface in card mode is inverted when tx_active is asserted (i.e. while transmission). Note: this bit is only valid in card mode. Note: if it ANT_ALM_AUTO_SWITCH_ENABLE is set this setting is ignored 6 ANT_ALM_AUTO_SWITCH_EN ABLE R/W 0 If set to 1, the ANT setting for ALM is switched automatically by HW. By default for ALM the ANT_short and ANT_mod uses the same settings as for PLM. 5 ANT_ALM_FW_RESET R/W 0 If set to 1 the ANT setting for ALM is reset to its initial receive configuration |
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