 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
OM25180FDKM Datasheet(PDF) 100 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
OM25180FDKM Datasheet(HTML) 100 Page - NXP Semiconductors |
|
|
100 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 100 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend 10 RX_ACTIVE This bit indicates activity of the RxDecoder. If 1 a data reception is ongoing; otherwise the RxDecoder is in idle state. 9:0 AGC_VALUE R 0*-3FFh Current value of the AGC 0h* Most sensitive: largest Rx-resistor, i.e., none of the switchable resistors are added in parallel 3FFh Most robust: smallest Rx-resistor, i.e., all switchable resistors are added in parallel Table 93. RF_STATUS register (address 001Dh) bit description …continued Bit Symbol Access Value Description Table 94. AGC_CONFIG register (address 001Eh) bit description Bit Symbol Access Value Description 16:31 RFU R 0* Reserved 14:15 AGC_VREF_SEL R/W 0* Select the set value for the AGC control:_ 00b: 1.15 V 01b: 1.40 V 10b: 1.50 V 11b: RFU 4:13 AGC_TIME_CONSTANT R/W 0* Time constant for the AGC update. An AGC period is given by (AGC_TIME_CONSTANT+1) * 13.56 MHz. The minimum allowed value for the AGC_TIME_CONSTANT is 4. 3 AGC_INPUT_SEL R/W 0* Selects the AGC value to be loaded into the AGC and the data source for fix-mode operation: 0b: AGC_VALUE_REG.AGC_CM_VALUE 1b: AGC_VALUE_REG.AGC.RM_VALUE 2 AGC_LOAD W 0* If set; the RX divider setting is loaded from AGC_VALUE_REG. AGC_INPUT_SEL defines the source of the data. This bit is automatically cleared. 1 AGC_MODE_SEL R/W 0* Selects the fix AGC value: 0b: Rx-divider is set according to AGC_VALUE_REG dependent on bit AGC_INPUT_SEL 1b: The last RX divider setting before AGC control operation had been deactivated is used (AGC_ENABLE_CONTROL=0, last RX divider setting is frozen). This bit is not causing any loading of new Rx-divider data. Set the bit AGC_LOAD for updating the RX divider with a new value. 0 AGC_ENABLE_CONTROL R/W 0* 0b: Fix mode operation. The RX divider is fixed to one value. The value is defined by AGC_MODE_SEL 1b: AGC control operation enabled |
Similar Part No. - OM25180FDKM |
|
Similar Description - OM25180FDKM |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
