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OM25180FDKM Datasheet(PDF) 97 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 97 Page - NXP Semiconductors |
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97 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 97 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend Table 90. SIGPRO_CONFIG register (address 001Ah) bit description Bit Symbol Access Value Description 3:31 RFU R 0 Reserved 2:0 BAUDRATE D 000*-111 Defines the baud rate of the receiving signal. The MSB is only relevant for reader mode. Note: These bits are set by the mode-detector if automatic mode detector is enabled and the communication mode is detected. 000* Reserved 001 Reserved 010 Reserved 011 Reserved 100 106 kBd This configuration is set by the Mode detector for ISO/IEC14443 type A and B. 101 212 kBd This configuration is set by the Mode detector for FeliCa 212 kBd. 110 424 kBd This configuration is set by the Mode detector for FeliCa 424 kBd. 111 848 kBd Table 91. SIGPRO_CM_CONFIG_REG register (address 001Bh) bit description Bit Symbol Access Value Description 31 RFU R 0 Reserved 29:30 RX_FRAMING Defines the framing in card mode. These bits are set by the Mode detector if automatic mode detection is enabled and the communication mode is detected. 00b: ISO14443-A / MIFARE 01b: ISO18092 (NFC - with Sync-byte 0xF0) 10b: FeliCa 11 ISO14443B 26:28 EDGE_DETECT_TAP_SEL Selects the number of taps of the edge-detector filter. 000b: Edge detector filter with 4 taps 001b: Edge detector filter with 6 taps 010b: Edge detector filter with 8 taps 011b: Edge detector filter with 8 taps 100b: Edge detector filter with 16 taps 101b: Edge detector filter with 18 taps 110b: Edge detector filter with 24 taps 111b: Edge detector filter with 32 taps 13:25 EDGE_DETECT_TH Threshold for the edge decision block of the ADCBCM. 0:12 BIT_DETECT_TH Threshold for the “bit” decision block of the ADCBCM. |
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