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OM25180FDKM Datasheet(PDF) 94 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 94 Page - NXP Semiconductors |
94 / 149 page ![]() PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 94 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend 15:5 RFU R 0 Reserved 4:1 TX_OVERSHOOT_PATTERN _LEN R/W 0*-Fh Defines length of the overshoot prevention pattern (value +1). The pattern is applied starting from the MSB of the defined pattern, all other bits are ignored. 0 TX_OVERSHOOT_PROT _ENABLE R/W 0*, 1 If set to 1, the overshoot protection is enabled. Table 85. TX_OVERSHOOT_CONFIG register (address 0015h) bit description …continued Bit Symbol Access Value Description Table 86. TX_DATA_MOD register (address 0016h) bit description Bit Symbol Access Value Description 8:15 TX_DATA_MOD_WIDTH R/W 0*-FFh Specifies the length of a pulse for sending data with miller pulse modulation enabled. The length is given by the number of carrier clocks + 1. 0:7 TX_BITPHASE R/W 0* - FFh Defines the number of 13.56 MHz cycles used for adjustment of TX_WAIT to meet the FDT. This is done by using this value as first counter initialization value instead of TX_WAIT_PRESCALER. These bits of TX_BITPHASE, together with TX_WAIT_VALUE and TX_WAIT_PRESCALER are defining the number of carrier frequency clocks which are added to the waiting period before transmitting data in all communication modes. TX_BITPHASE is used to adjust the TX bit synchronization during passive NFCIP-1 communication mode at 106 kbit and in ISO/IEC 14443A and 14443A/MIFARE card mode. |
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