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OM25180FDKM Datasheet(PDF) 92 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 92 Page - NXP Semiconductors |
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92 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 92 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend 5:3 RX_CRC_PRESET_SEL R/W 000b* Preset values of the CRC register for the Rx-Decoder. For a CRC calculation using 5bits, only the LSByte is used. 000b* 0000h, reset value. This configuration is set by the Mode detector for FeliCa. 001b 6363h, this configuration is set by the Mode detector for ISO14443 type A. 010b A671h 011b FFFFh, this configuration is set by the Mode detector for ISO14443 type B. 100b 0012h 101b E012h 110b RFU 111b Use arbitrary preset value RX_CRC_PRESET_VALUE 2 RX_CRC_TYPE R/W 0* Controls the type of CRC calculation for the Rx-Decoder 0 16-bit CRC calculation, reset value 1 5-bit CRC calculation 1 RX_CRC_INV R/W 0* Controls the comparison of the CRC checksum for the Rx-Decoder 0* Not inverted CRC value. This bit is cleared by the Mode detector for ISO14443 type A and FeliCa. 1 Inverted CRC value: F0B8h, this bit is set by the Mode detector for ISO14443 type B. 0 RX_CRC_ENABLE R/W 0* If set; the Rx-Decoder checks the CRC for correctness. Note: This bit is set by the Mode Detector when ISO14443 type B or FeliCa (212 kbit/s or 424 kbit/s) is detected. Table 82. CRC_RX_CONFIG (address 0012h) bit description …continued Bit Symbol Access Value Description Table 83. RX_STATUS_REG register (address 0013h) bit description Bit Symbol Access Value Description 26:31 RFU R 0 Reserved 19:25 RX_COLL_POS R 0* These bits show the bit position of the first detected collision in a received frame (only data bits are interpreted). Note: These bits shall only be interpreted in passive communication mode at 106 kbit/s or ISO/IEC14443 A /MIFARE reader / writer mode if bit CollPosValid is set to 1. Note: If RX_ALIGN is set to a value different to 0, this value is included in the RX_COLL_POS. 18 RX_COLLISION_DETECTED R 0* This flag is set to 1, when a collision has occurred. The position of the first collision is shown in the register RX_COLLPOS |
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