OM25180FDKM datasheet(85/149 Pages) NXP

Part #	OM25180FDKM

Description	High-performance multi-protocol full NFC Forum-compliant frontend

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Manufacturer	NXP [NXP Semiconductors]

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PN5180

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Product data sheet

COMPANY PUBLIC

Rev. 3.0 — 7 October 2016

240930

85 of 149

NXP Semiconductors

PN5180

High-performance multi-protocol full NFC Forum-compliant frontend

Table 69.

TRANSCEIVE_CONTROL register (address 0004h) bit description

Bit

Symbol

Access

Value

Description

4-9

STATE_TRIGGER_SELECT

R/W

000000*

Register to select the state to trigger the

STATE_CHANGE_IRQ flag. Each bit of the bit field

enables one state - several states are possible. Note:

If all bits are 0 no IRQ is triggered.

xxxxx1

IDLE state enabled to trigger IRQ

xxxx1x

WaitTransmit state enabled to trigger IRQ

xxx1xx

Transmitting state enabled to trigger IRQ

xx1xxx

WaitReceive state enabled to trigger IRQ

x1xxxx

WaitForData state enabled to trigger IRQ

1xxxxx

Receiving state enabled to trigger IRQ

3

TX_SKIP_SEND_ENABLE

R/W

0*, 1

If set, not transmission is started after tx_wait is

expired and START_SEND was set Note: The bit is

cleared by HW when the WaitReceive state is

entered.

2

TX_FRAMESTEP_ENABLE

R/W

0*, 1

If set, at every start of transmission; each byte of data

is sent in a separate frame. SOF and EOF are

appended to the data byte according to the framing

settings. After one byte is transmitted; the TxEncoder

waits for a new start trigger to continue with the next

byte.

1

RX_MULTIPLE_ENABLE

R/W

0*, 1

If set, the receiver is reactivated after the end of a

reception. A status byte is written to the RAM

containing all relevant status information of the frame.

Note: Data in RAM is word aligned therefore empty

bytes of a data Word in RAM are padded with 0x00

bytes. SW has to calculate the correct address for the

following frame.

0

INITIATOR

R/W

0*, 1

If set, the CLIF is configured for initiator mode.

Depending on this setting, the behavior of the

transceive command is different

Table 70.

PINCONFIG register (address 0005h) bit description

Bit

Symbol

Access

Value

Description

7

EN_SLEW_RATE_CONTROL

R/W

0*, 1

Enables slew rate control of digital pads

6

GPO7_DIR

R/W

0*, 1

Enables the output driver of GPO7. The GPO is only