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OM25180FDKM Datasheet(PDF) 43 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 43 Page - NXP Semiconductors |
43 / 149 page ![]() PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 43 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend 0x45 SEL_RES RW 1 7-0 Response to Select 0x46 FELICA_POLLING_RESPO NSE RW 18 - FeliCa Polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes system code) 0x51 RandomUID_enable RW 1 7-0 Enables the use of a RandomUID in card modes. If enabled (EEPROM configuration, Address 0x51), a random UID is generated after each RF-off. 0: Use UID stored in EEPROM 1: Randomly generate the UID 0x58 NFCID3 RW 1 7-0 NFCID3 (1 byte) If the Random UID is enabled (EEPROM address 0x51), this address contains the NFCID3. 0x59 DPC_CONTROL RW 1 7-0 Enables DPC and configures DPC gears 0 DPC_ENABLE cleared: OFF; set: ENABLE 3-1 GEAR_STEP_SIZE: binary definition of gear step size; position of Bit 1 is the LSB of gear step size 7-4 START_GEAR; binary definition of start gear, Position of bit 4 is the LSB of start gear number 0x5A DPC_TIME RW 2 15-0 Sets the value for the periodic regulation. Time base is 1/20 MHz. (Example: Value of 20000 is equal to 1 ms) 0x5C DPC_XI RW 1 7-0 Trim Value of the AGC value 0x5D AGC_CONTROL RW 2 Settings for AGC control loop 9-0 Duration 10 Duration enable 12-11 Step size 13 Step size enable 15-14 RFU 0x5F DPC_THRSH_HIGH RW 30 - Defines the AGC high threshold for each gear. DPC_AGC_GEAR_LUT_SIZE defines the number of gears. DPC_AGC_GEAR_LUT_SIZE can be 1..15. The threshold is defined by 2 bytes (bit0 located in the byte with lower address), 0x7D DPC_THRSH_LOW RW 2 15-0 Defines the AGC low threshold for initial gear. The threshold is defined by 2 bytes (bit 0 located in the byte with lower address) 0x7F DPC_DEBUG RW 1 7-0 Enables the debug signals 0x80 DPC_AGC_SHIFT_VALUE RW 1 7-0 Shift Value for the AGC dynamic low adoption to prevent oscillation 0x81 DPC_AGC_GEAR_LUT_ SIZE RW 1 7-0 Defines the number of gears for the lookup table (LUT, value can be between 1...15) 0x82 DPC_AGC_GEAR_LUT RW 15 - Defines the Gear Setting for each step size starting with Gear0 at lowest address up to 15 gears. Each entry contains a definition for the DPC_CONFIG register content. Bits 8:11 are not taken into account. Table 41. EEPROM Addresses …continued EEPROM Address (HEX) Field / Value Access Size (bytes) Bits Comments |
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