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OM25180FDKM Datasheet(PDF) 41 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 41 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend 0x34 LPCD_REFERENCE_ VALUE RW 2 15-0 AGC Reference Value 0x36 LPCD_FIELD_ON_TIME RW 1 7-0 1 byte delay * 8 in microseconds settling time for AGC measurement 0x37 LPCD_THRESHOLD RW 1 7-0 1 byte AGC threshold value which is used to compare against the (Current AGC value – Reference AGC) during the Low-Power Card Detection phase 0x38 up to firmware version 3.5: LPCD_REFVAL_CONTROL RW 1 7-0 Configures the LPCD mode and reference value for antenna detuning by card / metal 1-0 LPCD Mode 00b - Use EEPROM value of LPCD_REFERENCE_VALUE for reference value 01b - Use on begin of an LPCD a measurement cycle for generating a reference value. 10b - Use the Register value of CHECK_CARD_RESULT for reference value. This allows the configuration of the reference value without EEPROM programming. 2 GPO1 Control for external TVDD LDO 0b - Disable Control of external TVDD LDO via GPO1 1b - Enable Control of external TVDD LDO via GPO1 from firmware version 3.6 onwards: LPCD_REFVAL_GPO_CO NTROL RW 1 7-0 This byte in EEPROM is used to control the GPIO assertion during wake-up and LPCD card detect. Table 41. EEPROM Addresses …continued EEPROM Address (HEX) Field / Value Access Size (bytes) Bits Comments |
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