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OM25180FDKM Datasheet(PDF) 40 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 40 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend 0x1A IRQ_PIN_CONFIG RW 1 7-0 Configures the state (active high/low) and clearing conditions for the IRQ pin 0 Cleared: IRQ active low Set: IRQ active high 1 Cleared: Use IRQ_SET_CLEAR_REG to clear IRQ pin Set: Auto Clear on Read of IRQ_STATUS_REG 0x1B MISO_PULLUP_ENABLE RW 1 7-0 Configures the pullup resistor for the SPI MISO 2-0 000b - no pulldown 001b - no pullup 010b - pulldown 011b - pullup 7-3 04h - FFh RFU 0x1C PLL_DEFAULT_SETTING RW 8 PLL configuration of clock input frequency in case a 13.56 MHz Crystal is not used. The PLL setting need to be written as two 4-byte words to the memory, little endian. This means that the e.g the value for 8 MHz (03A3531002A12210) shall be written as follows to the EPROM (ascending addresses starting at 0x1C): 10 53 A3 0310 22 A1 02 8 MHz: 03A35310 - 02A12210 12 MHz: 02A38288 - 02E10190 16 MHz: 02E2A1D8 - 02D11150 24 MHz: 02D35138 - 02E0E158 (default) 0x24 PLL_DEFAULT_SETTING_ ALM R/W 8 - PLL configuration for the Active Load Modulation 0x2c PLL_LOCK_SETTING R/W 4 31-0 Lock Settings for the PLL - do not change 0x30 CLOCK_CONFIG RW 1 7-0 Configures the source of the clock, either 27.12 MHz crystal or external clock e.g. 24 MHz with PLL refactoring 3-0 0000b - PLL 1000b - Crystal 7-4 RFU 0x31 RFU RW 1 7-0 - 0x32 MFC_AUTH_TIMEOUT RW 2 15-0 Timeout value used for each of the Auth1 & Auth2 stages during MFC Authenticate (MIFARE Authenticate). This is an unsigned 16-bit integer value in little endian order. The timebase for the timeout is 1.0 microseconds. Example: The default value of 0x0, 0x5 refers actually to 0x500 (1280 decimal) resulting in a timeout of 1.28 ms for each of the authentication stages. Table 41. EEPROM Addresses …continued EEPROM Address (HEX) Field / Value Access Size (bytes) Bits Comments |
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