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OM25180FDKM Datasheet(PDF) 39 Page - NXP Semiconductors |
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OM25180FDKM Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 149 page  PN5180 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.0 — 7 October 2016 240930 39 of 149 NXP Semiconductors PN5180 High-performance multi-protocol full NFC Forum-compliant frontend Attention: Test bus must be enabled before in the EEPROM settings (EEPROM address: 0x17, TESTBUS_ENABLE). The host interface shall use the following sequence: 11.5 Memories 11.5.1 Overview The PN5180 implements two different memories: EEPROM and RAM. At start-up, all registers are initialized with default values. For the registers defining the RF functionality, the default values are not set to execute any contactless communication. The registers defining the RF functionality are initialized by using the instruction LOAD_RF_CONFIGURATION. Using the instruction LOAD_RF_CONFIGURATION, the initialization of the registers which define the RF behavior of the IC performs an automatic copy of a predefined EEPROM area (read/write EEPROM section1 and section2, register reset) into the registers defining the RF behavior. 11.5.2 EEPROM The EEPROM memory maintains its content during Power-OFF, whereas the RAM (Buffers) does not keep any data stored in this volatile memory. The EEPROM address range is from 0x00 to 0xFF. The EEPROM contains information about Die Identifier, Firmware Version, System configuration and RF settings for fast configuration. Table 41. EEPROM Addresses EEPROM Address (HEX) Field / Value Access Size (bytes) Bits Comments 0x00 Die identifier R 16 - Each DIE has a unique Identifier 0x10 Product Version R 2 15-0 Product Version Indicator 0x12 Firmware Version R 2 15-0 Firmware Version 0x14 EEPROM Version R 2 15-0 EEPROM Version Number (default initialization values) 0x16 IDLE_IRQ_AFTER_BOOT RW 1 7-0 This enables the IDLE IRQ to be set after the boot has finished 0x17 TESTBUS_ENABLE RW 1 7-0 If bit 7 is set, the test bus functionality is enabled. During this phase, it can happen that the BUSY line is asserted after the frame is received. Therefore it is recommended to first set NSS to low, wait until BUSY goes high and then send the data. 0x18 XTAL_BOOT_TIME RW 2 15-0 XTAL boot time in us |
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