Philips Semiconductors

Product data

SCC68681

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

3

PIN CONFIGURATIONS

1

39

17

28

40

29

18

7

PLCC

6

PIN/FUNCTION

1

NC

16 OP5

31 OP2

2

A1

17 OP7

32 OP0

3

IP3

18 D1

33 TxDA

4A2

19 D3

34 NC

5

IP1

20 D5

35 RxDA

6

A3

21 D7

36 X1/CLK

7

A4

22 GND

37 X2

8

IP0

23 NC

38 RESETN

9

R/WN

24 INTRN

39 CSN

10 DTACKN

25 D6

40 IP2

11

RxDB

26 D4

41 IACKN

12 NC

27 D2

42 IP5

13 TxDB

28 D0

43 IP4

14 OP1

29 OP6

15 OP3

30 OP4

24

23

22

21

20

19

18

17

16

15

28

27

12

10

11

9

8

7

6

5

4

3

2

1

14

13

26

25

29

30

31

32

33

34

35

36

37

38

39

40

DIP

VCC

IP4

IP5

IACKN

IP2

CSN

RESETN

X2

X1/CLK

RxDA

TxDA

OP0

OP2

OP4

OP6

D0

D2

D4

D6

INTRN

A1

IP3

A2

IP1

A3

A4

IP0

R/WN

DTACKN

RxDB

TxDB

OP1

OP3

OP5

OP7

D1

D3

D5

D7

GND

SD00107

Figure 1. Pin Configurations

PIN DESCRIPTION

SYMBOL

PIN

TYPE

NAME AND FUNCTION

PLCC44

DIP40

D0–D7

28, 18,

27, 19,

26, 20,

25, 21

25, 16,

24, 17,

23, 18,

22, 19

I/O

Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between

the DUART and the CPU. D0 is the least significant bit.

CSN

39

35

I

Chip Select: Active-LOW input signal. When LOW, data transfers between the CPU and the

DUART are enabled on D0–D7 as controlled by the R/WN, RDN and A1–A4 inputs. When HIGH,

places the D0–D7 lines in the 3-State condition.

R/WN

9

8

I

Read/Write: A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a

cycle is initiated by assertion of the CSN input.

A1–A4

2, 4, 6, 7

1, 3, 5, 6

I

Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESETN

38

34

I

Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the

IVR to hex 0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channel A and

B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test

modes, sets MR pointer to MR1.

DTACKN

10

9

O

Data Transfer Acknowledge: Three-state active LOW output asserted in write, read, or interrupt

cycles to indicate proper transfer of data between the CPU and the DUART.

INTRN

24

21

O

Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or more of

the eight maskable interrupting conditions are true.

IACKN

41

37

I

Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In

response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it

has an interrupt pending.