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SCC68681C1A44 Datasheet(PDF) 19 Page - NXP Semiconductors |
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SCC68681C1A44 Datasheet(HTML) 19 Page - NXP Semiconductors |
19 / 29 page ![]() Philips Semiconductors Product data SCC68681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 19 Transmitter Disable Note The sequence of instructions enable transmitter — load transmit holding register — disable transmitter will result in nothing being sent if the time between the end of loading the transmit holding register and the disable command is less that 3/16 bit time in the 16 × mode or one bit time in the 1× mode. Also, if the transmitter, while in the enabled state and underrun condition, is immediately disabled after a single character is loaded to the transmit holding register, that character will not be sent. In general, when it is desired to disable the transmitter before the last character is sent AND the TxEMT bit is set in the status register (TxEMT is always set if the transmitter has underrun or has just been enabled), be sure the TxRDY bit is active immediately before issuing the transmitter disable instruction. TxRDY sets at the end of the ‘start bit’ time. It is during the start bit that the data in the transmit holding register is transferred to the transmit shift register. Non-standard baud rates are available as shown in Table 6 below, via the BRG Test function. Table 6. Baud Rates Extended Normal BRG BRG Test CSR[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1 0000 50 75 4,800 7,200 0001 110 110 880 880 0010 134.5 134.5 1,076 1,076 0011 200 150 19.2 k 14.4 k 0100 300 300 28.8 k 28.8 k 0101 600 600 57.6 k 57.6 k 0110 1,200 1,200 115.2 k 115.2 k 0111 1,050 2,000 1,050 2,000 1000 2,400 2,400 57.6 k 57.6 k 1001 4,800 4,800 4,800 4,800 1010 7,200 1,800 57.6 k 14.4 k 1011 9,600 9,600 9,600 9,600 1100 38.4 k 19.2 k 38.4 k 19.2 k 1101 Timer Timer Timer Timer 1110 I/O2 – 16 × I/O2 – 16 × I/O2 – 16 × I/O2 – 16 × 1111 I/O2 – 1 × I/O2 – 1 × I/O2 – 1 × I/O2 – 1 × NOTE: Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication. The test mode at address H‘A’ changes all transmitters and receivers to the 1 × mode and connects the output ports to some internal nodes. Receiver Reset in the Normal Mode (Receiver Enabled) Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data, status and programming will be preserved and available before reset. The reset will NOT affect the programming. Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11) Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before reset. The reset will NOT affect other programming. The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by the partial enabling of the receiver. SD00097 |
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