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SCC68681C1A44 Datasheet(PDF) 16 Page - NXP Semiconductors |
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SCC68681C1A44 Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 29 page  Philips Semiconductors Product data SCC68681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 16 ACR – Auxiliary Control Register ACR[7] – Baud Rate Generator Set Select This bit selects one of two sets of baud rates to be generated by the BRG: Set 1: 50, 110, 134.5, 200, 300, 600, 1.05 k, 1.2 k, 2.4 k, 4.8 k, 7.2 k, 9.6 k, and 38.4 k baud. Set 2: 75, 110, 134.5, 150, 300, 600, 1.2 k, 1.8 k, 2.0 k, 2.4 k, 4.8 k, 9.6 k, and 19.2 k baud. See Table 6 for other rates to 115.2 k baud. The selected set of rates is available for use by the Channel A and B receivers and transmitters as described in CSRA and CSRB. Baud rate generator characteristics are given in Table 4. ACR[6:4] – Counter/Timer Mode And Clock Source Select This field selects the operating mode of the counter/timer and its clock source as shown in Table 5. Table 5. ACR 6:4 Field Definition ACR[6:4] MODE CLOCK SOURCE 000 Counter External (IP2)* 001 Counter TxCA – 1 × clock of Channel A transmitter 010 Counter TxCB – 1 × clock of Channel B transmitter 011 Counter Crystal or external clock (x1/CLK) divided by 16 100 Timer (square wave) External (IP2)* 101 Timer (square wave) External (IP2) divided by 16* 110 Timer (square wave) Crystal or external clock (X1/CLK) 111 Timer (square wave) Crystal or external clock (X1/CLK) divided by 16 NOTE: * In these modes, the Channel B receiver clock should normally be generated from the baud rate generator. Timer mode generates squarewave. ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR[7]) to be set. If a bit is in the ‘on’ state the setting of the corresponding bit in the IPCR will also result in the setting of ISR[7], which results in the generation of an interrupt output if IMR[7] = 1. If a bit is in the ‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7]. IPCR – Input Port Change Register IPCR[7] – IP3, IP2, IP1, IP0 Change-of-State These bits are set when a change-of-state, as defined in the input port section of this data sheet, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. IPCR[3:0] – IP3, IP2, IP1, IP0 Current State These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. ISR – Interrupt Status Register This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is also a ‘1’, the INTRN output will be asserted (LOW). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 0016 when the DUART is reset. ISR[7] – Input Port Change Status This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR. ISR[6] – Channel B Change In Break This bit, when set, indicates that the Channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel B ‘reset break change interrupt’ command. ISR[5] – Channel B Receiver Ready or FIFO Full The function of this bit is programmed by MR1B[6]. If programmed as receiver ready, it indicates that a character has been received in Channel B and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the RHR. If after this read there are more characters still in the FIFO the bit will be set again after the FIFO is ‘popped’. If programmed as FIFO full, it is set when a character is transferred from the receive holding register to the receive FIFO and the transfer caused the Channel B FIFO to become full; i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR. If a character is waiting in the receive shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO. ISR[4] – Channel B Transmitter Ready This bit is a duplicate of TxRDYB (SRB[2]). ISR[3] – Counter Ready. In the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches zero count). The bit is reset by a stop counter command. The command, however, does not stop the counter/timer. ISR[2] – Channel A Change in Break This bit, when set, indicates that the Channel A receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel A ‘reset break change interrupt’ command. ISR[1] – Channel A Receiver Ready Or FIFO Full The function of this bit is programmed by MR1A[6]. If programmed as receiver ready, it indicates that a character has been received in Channel A and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU read the RHR. If after this read there are more characters still in the FIFO the bit will be set again after the FIFO is ‘popped’. If programmed as FIFO full, it is set when a character is transferred from the receive holding register to the |
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