Philips Semiconductors

Product data

SCC68681

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

21

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

Reset Timing (See Figure 3)

RESETN pulse width

200

ns

Bus Timing (See Figures 4, 5, 6)

A1–A4 setup time to CSN LOW

10

–

–

ns

A1–A4 hold time from CSN LOW

100

–

–

ns

RWN setup time to CSN HIGH

0

–

–

ns

RWN hold time to CSN HIGH

0

–

–

ns

CSN HIGH pulse width

90

–

–

ns

CSN or IACKN HIGH from DTACKN LOW

20

–

–

ns

Data valid from CSN or IACKN LOW

–

–

175

ns

–

–

100

ns

Data setup time to CLK HIGH

100

–

–

ns

Data hold time from CSN HIGH

20

–

–

ns

DTACKN LOW from read data valid

0

–

–

ns

DTACKN LOW (read cycle) from CLK HIGH

–

–

125

ns

DTACKN LOW (write cycle) from CLK HIGH

–

–

125

ns

DTACKN HIGH from CSN or IACKN HIGH

–

–

100

ns

DTACKN HIGH impedance from CSN or IACKN HIGH

–

–

125

ns

CSN or IACKN setup time to clock HIGH

90

–

–

ns

Port Timing (See Figure 7)

Port input setup time to CSN LOW

0

–

–

ns

Port input hold time from CSN HIGH

0

–

–

ns

Port output valid from CSN HIGH

–

–

400

ns

Interrupt Reset Timing (See Figure 9)

INTRN or OP3–OP7 when used as interrupts negated from:

Read RHR (RxRDY/FFULL interrupt)

–

–

300

ns

Write THR (TxRDY interrupt)

–

–

300

ns

Reset command (delta break interrupt)

–

–

300

ns

IR

Stop C/T command (counter interrupt)

–

–

300

ns

Read IPCR (input port change interrupt)

–

–

300

ns

Write IMR (clear of interrupt mask bit)

–

–

300

ns

Clock Timing (See Figure 8)

X1/CLK HIGH or LOW time

100

–

–

ns

X1/CLK frequency

0

3.6864

4.0

MHz

CTCLK HIGH or LOW time

100

–

–

ns

CTCLK frequency

0

–

4.0

MHz

RxC HIGH or LOW time

220

–

–

ns

RxC frequency

(16

×)

0

–

2.0

MHz

RX

(1

×)

0

–

1.0

MHz

TxC HIGH or LOW time

220

–

–

ns

TxC frequency

(16

×)

0

–

2.0

MHz

TX

(1

×)

0

–

1.0

MHz

Transmitter Timing (See Figure 10)

TxD output delay from TxC external clock input on IP pin

–

–

350

ns

Output delay from TxC LOW at OP pin to TxD data output

–

–

150

ns

Receiver Timing (See Figure 11)

RxD data setup time before RxC HIGH at external clock input on IP pin

240

–

–

ns

RxD data hold time after RxC HIGH at external clock input on IP pin

200

–

–

ns

NOTES:

range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with

a transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input

voltages of 0.8 V and 2.0 V as appropriate.

3. Typical values are at +25

°C, typical supply voltages, and typical processing parameters.

5. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus reads are not performed.

Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

6. This specification imposes a lower bound on CSN and IACKN LOW, guaranteeing that it will be LOW for at least 1 CLK period. This

requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.

7. This spec is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram,

not to guarantee operation of the part. If setup time is violated, DTACKN may be asserted as shown, or may be asserted 1 clock cycle later.

8. Operation to 0 MHz is assured by design. Minimum test frequency is 2.0 MHz.