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SCC68681 Datasheet(PDF) 13 Page - NXP Semiconductors |
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SCC68681 Datasheet(HTML) 13 Page - NXP Semiconductors |
13 / 29 page ![]() Philips Semiconductors Product data SCC68681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 13 CSRB – Channel B Clock Select Register CSRB[7:4] – Channel B Receiver Clock Select This field selects the baud rate clock for the Channel B receiver. The field definition is as shown in Table 3, except as follows: CSRB[7:4] Baud Rate CSRB[7:4] ACR[7] = 0 ACR[7] = 1 1110 1111 IP2–16 × IP2–1 × IP2–16 × IP2–1 × The receiver clock is always a 16 × clock except for CSRB[7:4] = 1111. CSRB[3:0] – Channel B Transmitter Clock Select This field selects the baud rate clock for the Channel B transmitter. The field definition is as shown in Table 3, except as follows: CSRB[3:0] Baud Rate CSRB[3:0] ACR[7] = 0 ACR[7] = 1 1110 1111 IP5–16 × IP5–1 × IP5–16 × IP5–1 × The transmitter clock is always a 16 × clock except for CSRB[3:0] = 1111. CRA – Channel A Command Register CRA is a register used to supply commands to Channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word. CRA[7] – Not Used Should be set to zero for upward compatibility with newer parts. CRA[6:4] – Miscellaneous Commands The encoded value of this field may be used to specify a single command as follows: CRA[6:4] – COMMAND NOTE: Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. 000 No command. 001 Reset MR pointer. Causes the Channel A MR pointer to point to MR1. 010 Reset receiver. Resets the Channel A receiver as if a hardware reset had been applied. The receiver is disabled and the FIFO is flushed. 011 Reset transmitter. Resets the Channel A transmitter as if a hardware reset had been applied. 100 Reset error status. Clears the Channel A Received Break, Parity Error, and Overrun Error bits in the status register (SRA[7:4]). Used in character mode to clear OE status (although RB, PE and FE bits will also be cleared) and in block mode to clear all error status after a block of data has been received. 101 Reset Channel A break change interrupt. Causes the Channel A break detect change bit in the interrupt status register (ISR[2]) to be cleared to zero. 110 Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the start of the break condition will be delayed up to two bit times. If the transmitter is active the break begins when transmission of the character is completed. If a character is in the THR, the start of the break will be delayed until that character, or any other loaded subsequently are transmitted. The transmitter must be enabled for this command to be accepted. 111 Stop break. The TxDA line will go HIGH (marking) within two bit times. TxDA will remain HIGH for one bit time before the next character, if any, is transmitted. CRA[3] – Disable Channel A Transmitter This command terminates transmitter operation and reset the TxDRY and TxEMT status bits. However, if a character is being transmitted or if a character is in the THR when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state. CRA[2] – Enable Channel A Transmitter Enables operation of the Channel A transmitter. The TxRDY status bit will be asserted. CRA[1] – Disable Channel A Receiver This command terminates operation of the receiver immediately – a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. If the special multidrop mode is programmed, the receiver operates even if it is disabled. See Operation section. CRA[0] – Enable Channel A Receiver Enables operation of the Channel A receiver. If not in the special wake-up mode, this also forces the receiver into the search for start-bit state. Note: Performing a Disable and Enable at the same time results in Disable. CRB – Channel B Command Register CRB is a register used to supply commands to Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word. The bit definitions for this register are identical to the bit definitions for CRA, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs., SRA – Channel A Status Register SRA[7] – Channel A Received Break This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received further entries to the FIFO are inhibited until the RxDA line to the marking state for at least one-half a bit time two successive edges of the internal or external 1 × clock. This will usually require a HIGH time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. When this bit is set, the Channel A ‘change in break’ bit in the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry can detect breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. SRA[6] – Channel A Framing Error This bit, when set, indicates that a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. SRA[5] – Channel A Parity Error This bit is set when the ‘with parity’ or ‘force parity’ mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In the special multidrop mode the parity error bit stores the receive A/D bit. |
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