TPS61222-EP

SLVSBI2 – SEPTEMBER 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE

PART NUMBER

VID NUMBER

MARKING

–55°C to 125°C

SHL

6-Pin SC-70

TPS61222MDCKTEP

V62/12603-01XE

(1)

Contact the factory to check availability of other fixed output voltage versions.

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

Input voltage range on VIN, L, VOUT, EN, FB

–0.3 to 7.5

V

Operating junction temperature range

–55 to 145

°C

Storage temperature range

–65 to 150

°C

2

kV

ESD

200

V

1.5

kV

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TPS61222

DCK

UNITS

6 PINS

231.2

61.8

78.8

°C/W

2.2

78

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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