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GS9092A Datasheet(PDF) 33 Page - Semtech Corporation |
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GS9092A Datasheet(HTML) 33 Page - Semtech Corporation |
33 / 61 page GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Final Data Sheet 34715 - 5 February 2013 33 of 61 Figure 3-7: Ancillary Data Insertion %% ANC_DATA_SWITCH = HIGH ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to second half of FIFO starting at adress zero. Application layer continues to read from the first half of the FIFO. Application layer read pointer Internal write pointer 0 1023 1023 0 Application layer read pointer Internal write pointer 0 0 1023 1023 ANC_DATA_SWITCH = LOW 0 1023 Internal write pointer Application layer read pointer ANC_DATA_SWITCH = HIGH 0 1023 ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to first half of FIFO starting at address zero. Application layer continues to read from second half of FIFO. Toggling ANC_DATA_SWITCH back LOW will clear the second half of the FIFO and go back the situation depicted in box A. Application layer read pointer Internal write pointer %% 0 ANC_DATA_SWITCH = LOW 1023 0 1023 ANC_DATA_SWITCH toggled LOW. First half of FIFO cleared and ancillary data read from second half of FIFO. Device continues to write ancillary data to second half of FIFO. A B C D ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA ANC_DATA NOTE: At least 1100 PCLK cycles must pass between toggles of the ANC_DATA_SWITCH bit. |
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