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GS9092A Datasheet(PDF) 31 Page - Semtech Corporation |
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GS9092A Datasheet(HTML) 31 Page - Semtech Corporation |
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31 / 61 page  GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Final Data Sheet 34715 - 5 February 2013 31 of 61 Once the above steps are completed, the application layer may set the ANC_PKT_INS bit of the IOPROC_DISABLE register HIGH (see Table 3-4 in Packet Generation and Insertion on page 37) to enable insertion of the prepared ancillary packets into the video data stream. Ancillary data packets will be inserted in the following frame after the ANC_PKT_INS bit has been set HIGH. Note: When inserting ancillary data into the blanking region, the total number of words cannot exceed the size of the blanking region, and the data count value in the packet must be correct. 3.3.3.1 Ancillary Data Insertion Once the ANC_PKT_INS bit is set HIGH, the device will start reading the user programmed ancillary packets out of the FIFO and insert them into the video stream. Subsequent ancillary packets programmed by the application layer will continue to be placed into the first half of the FIFO until the ANC_DATA_SWITCH bit is toggled (see block A of Figure 3-7). By default, the ANC_DATA_SWITCH bit of the IO_CONFIG register is set LOW. When ANC_DATA_SWITCH is toggled from LOW to HIGH, any new ancillary data the application layer programs will be placed in the second half of the FIFO. The device will continue to insert ancillary data from the first half of the FIFO into the video stream (see block B of Figure 3-7). Once the ancillary data in the first half of the FIFO has been inserted into the video stream, ANC_DATA_SWITCH may be toggled again. This will clear the first half of the FIFO and begin insertion of ancillary data from the second half of the FIFO. The application layer may continue programming ancillary data into the second half of the FIFO (see block C of Figure 3-7). If the ANC_DATA_SWITCH bit is toggled again, any new data the application layer programs will be placed into the first half of the FIFO. The device will continue to insert ancillary data from the second half of the FIFO into the video stream (see block D of Figure 3-7). Toggling ANC_DATA_SWITCH again will clear the second half of the FIFO and restore the read and write pointers to the situation shown in block A. The switching process (shown in blocks A to D in Figure 3-7) will continue with each toggle of the ANC_DATA_SWITCH bit. Note: At least 1100 PCLK cycles (41us) must pass between toggles of the ANC_DATA_SWITCH bit. The GS9092A will insert the ancillary data programmed in the FIFO into each video frame at the designated line(s) programmed in ANC_LINE_A[10:0] and/or ANC_LINE_B[10:0]. Clearing the ANC_PKT_INS bit will not automatically disable ancillary data insertion. To disable ancillary data insertion, switch the FIFO into bypass mode by setting FIFO_MODE[1:0] = 11b. 2200 PCLK cycles after the device re-enters ancillary data insertion mode, data extraction will commence immediately if ANC_PKT_INS is HIGH. When there are existing ancillary data packets present in the video data stream, the device will append the ancillary data to the existing data only when the ANC_SAV bit is set LOW. In this case, all existing ancillary data must be contiguous after the EAV. If data |
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