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GS9092A Datasheet(PDF) 28 Page - Semtech Corporation |
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GS9092A Datasheet(HTML) 28 Page - Semtech Corporation |
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28 / 61 page  GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Final Data Sheet 34715 - 5 February 2013 28 of 61 To allow larger K28.5 packet sizes to be inserted, a write pointer offset can be programmed into the FIFO_EMPTY_OFFSET[9:0] register of the host interface. If an offset value is programmed in this register, the FIFO_EMPTY flag is set HIGH when the read and write pointers of the FIFO are at the same address, and will remain HIGH until the write pointer reaches the programmed offset. While the FIFO_EMPTY flag is HIGH, the device will continue to insert stuffing characters. Once the pointer offset has been exceeded, the FIFO_EMPTY flag will go LOW and the device will begin reading MPEG data out of the FIFO (see box B of Figure 3-6). In the case where the read pointer is originally ahead of the write pointer, the FIFO_FULL flag will be set HIGH when both pointers arrive at the same address (see box C of Figure 3-6). The application layer can use this flag to determine when to write to the device. A read and write pointer offset may also be programmed in the FIFO_FULL_OFFSET[9:0] register of the host interface. If an offset value is programmed in this register, the FIFO_FULL flag will be set HIGH when the read and write pointers of the FIFO are at the same address, and will remain set HIGH until the read pointer reaches the programmed offset. Once the pointer offset has been exceeded, the FIFO_FULL flag will be cleared (see box D of Figure 3-6). Note: When the FIFO is configured for DVB-ASI mode, the INSSYNCIN pin is unused, as synchronization characters are inserted based on the FIFO status flags. The pin should be grounded. When the internal FIFO is bypassed in DVB-ASI mode, the INSSYNCIN input assumes normal operation as described in Control Signal Inputs on page 35. Gating the WR_CLK Using the FIFO_FULL Flag Using the asynchronous FIFO_FULL flag to gate the WR_CLK requires external clock gating circuitry to generate a clean burst clock (see Figure 3-4). An example circuit for this application is shown in Figure 3-5. Figure 3-4: Burst Clock CORRECT INCORRECT |
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Similar Description - GS9092A |
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