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GS9092A Datasheet(PDF) 26 Page - Semtech Corporation |
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GS9092A Datasheet(HTML) 26 Page - Semtech Corporation |
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26 / 61 page  GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Final Data Sheet 34715 - 5 February 2013 26 of 61 3.3.1 Video Mode The internal FIFO is in video mode under the following conditions: • the FIFO_EN and IOPROC_EN pins are set HIGH, • the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register (Table 3-4) are configured to 00b, • the DETECT_TRS pin is set LOW; and • TRS insertion, EDH correction/insertion, illegal code re-mapping, and SMPTE packet insertion are all disabled (i.e. bits 0, 2, 3, and 4 of the IOPROC_DISABLE register are set HIGH). Note: The FIFO will still enter video mode if any of bits 0, 2, 3, or 4 of the IOPROC_DISABLE register are LOW; however, the output video data will contain errors. By default, the FIFO_MODE[1:0] bits are set to 00b by the device whenever the SMPTE_BYPASS pin is set HIGH and the DVB_ASI and DETECT_TRS pins are set LOW. In video mode, the H, V, and F pins become input signals that must be supplied by the user. Figure 3-2 shows the input and output signals of the FIFO when it is configured for video mode. Figure 3-2: FIFO in Video Mode When operating in video mode, the GS9092A will read data sequentially from the FIFO, starting with the first active pixel in location zero of the memory. In this mode, it is possible to use the FIFO for clock phase interchange and data delay. The device will ensure read-side synchronization is maintained, according to the supplied PCLK and supplied H, V, and F timing information. Full write-control of the FIFO is made available to the application interface such that data is clocked into the FIFO on the rising edge of the externally provided WR_CLK. The FIFO write pointer will be reset to position zero of the memory when there is a HIGH-to-LOW transition at the WR_RESET pin. The application layer must start writing the first active pixel of the line into location zero of memory. Therefore, the user should use the WR_RESET pin to reset the FIFO write pointer prior to writing to the device. Note: The BLANK signal must not be asserted in video mode. WR_CLK FIFO (Video Mode) RD_CLK (PCLK) 10-bit Video Data 10-bit Video Data WR_RESET RD_RESET (supplied H timing) Application Interface Internal |
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