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GS9092A Datasheet(PDF) 55 Page - Semtech Corporation |
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GS9092A Datasheet(HTML) 55 Page - Semtech Corporation |
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55 / 61 page  GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Final Data Sheet 34715 - 5 February 2013 55 of 61 3.14 JTAG Operation When the JTAG/HOST pin is set HIGH by the application layer, the host interface port (as described in GSPI Host Interface on page 51) will be configured for JTAG test operation. In this mode, pins 16, 17, 19, and 20 become TMS, TCK, TDO, and TDI respectively. In addition, the RESET pin will operate as the test reset pin, as well as resetting the internal registers. Boundary scan testing using the JTAG interface will be possible in this mode. There are two methods in which JTAG can be used on the GS9092A: 1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test Equipment) during PCB assembly; or 2. Under control of the host for applications such as system power self tests. When the JTAG tests are applied by ATE, care must be taken to disable any other devices driving the digital I/O pins. If the tests are to be applied only at ATE, this can be accomplished with tri-state buffers used in conjunction with the JTAG/HOST input signal. This is shown in Figure 3-17. Alternatively, if the test capabilities are to be used in the system, the host may still control the JTAG/HOST input signal, but some means for tri-stating the host must exist in order to use the interface at ATE. This is represented in Figure 3-18. Figure 3-17: In-Circuit JTAG Figure 3-18: System JTAG Application HOST GS9092A CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG_EN In-circuit ATE probe Application HOST GS9092A CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG_EN In-circuit ATE probe Tri-State |
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