GS9092A datasheet(50/61 Pages) SEMTECH

Part #	GS9092A

Description	270Mb/s Serializer for SDI and DVB-ASI

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GS9092A GenLINX® III 270Mb/s Serializer for SDI and

DVB-ASI

Final Data Sheet

34715 - 5

February 2013

50 of 61

and 101b respectively) is programmed into the IO_CONFIG registers when the device is

in SMPTE mode, the value will be ignored and the I/O pin will be set to a high impedance

state.

3.12 Low Latency Mode

When the IOPROC_EN pin is set LOW, the GS9092A will enter a low-latency mode such

that the serial digital data will be output with the minimum PCLK latency possible. The

FIFO and all processing blocks except the SMPTE scrambling block will be bypassed

when SMPTE_BYPASS is HIGH.

Low-latency mode will also be selected when SMPTE_BYPASS is set LOW, regardless of

the setting of the IOPROC_EN signal (see Table 3-12).

In DVB-ASI mode (DVB-ASI Mode on page 35), the device will have a higher latency

then low-latency mode, although this latency will be less than SMPTE mode (SMPTE

Mode on page 34).

Table 3-11: STAT [2:0] Output Default Configuration

Device Configuration

IO_CONFIG Register

I/O

Function

Default IO_CONFIG

Setting

SMPTE Functionality

SMPTE_BYPASS = HIGH

DVB_ASI = LOW

FIFO: Video Mode or Ancillary

Data Insertion Mode

STAT0_CONFIG

I/O

H

000b

STAT1_CONFIG

I/O

V

001b

STAT2_CONFIG

I/O

F

010b

DVB-ASI

DVB_ASI = HIGH

FIFO: DVB-ASI Mode

STAT0_CONFIG

Output

FIFO_FULL

110b

STAT1_CONFIG

Output

FIFO_EMPTY

111b

STAT2_CONFIG

Output

High Z

000b

Data-Through

SMPTE_BYPASS = LOW

DVB_ASI = LOW

STAT0_CONFIG

Output

High Z

000b

STAT1_CONFIG

Output

High Z

000b

STAT2_CONFIG

Output

High Z

000b

Table 3-12: Pin Settings in Low-latency Mode

IOPROC_EN Setting

SMPTE_BYPASS Setting

Latency

(PCLK Cycles)

LOW

9

HIGHLOW

10

LOW

HIGH8

HIGHHIGH21

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