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GS9092A Datasheet(PDF) 41 Page - Semtech Corporation

Part # GS9092A
Description  270Mb/s Serializer for SDI and DVB-ASI
Download  61 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS9092A Datasheet(HTML) 41 Page - Semtech Corporation

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GS9092A GenLINX® III 270Mb/s Serializer for SDI and
DVB-ASI
Final Data Sheet
34715 - 5
February 2013
41 of 61
By default, after a system reset, the GS9092A will calculate the EDH ranges based on the
setting of the DETECT_TRS pin. If DETECT_TRS is LOW, the device will calculate the
EDH ranges based on the received H, V, and F timing. If DETECT_TRS is HIGH, the device
will calculate the ranges based on the internal TRS timing.
Alternatively, the user can program the EDH calculation ranges in the host interface.
The registers available to the host interface for programming EDH calculation ranges
include active picture and full field line start and end positions for both fields. Table 3-7
shows the relevant registers, which default to '0' after device reset.
If any or all of these register values are zero, then the EDH CRC calculation ranges will
be determined from the flywheel generated H signal. The first AP pixel will always be
the first pixel after the SAV TRS code words. The first FF pixel will always be the first
pixel after the EAV TRS code words. The last AP pixel and last FF pixel will always be the
last pixel before the start of the EAV code words. Figure 3-9 shows the positions of the
FF and AP pixel positions relative to TRS words and H timing.
Figure 3-9: First and Last FF and AP Pixel Positions
EDH error flags (EDH, EDA, IDH, IDA, and UES) for ancillary data, full field, and active
picture will also be inserted. These flags must be programmed into the EDH_FLAG
registers of the device by the application layer (Table 3-8).
Note 1:
It is the responsibility of the user to ensure that the EDH flag registers are
updated once per field.
The prepared EDH packet will be inserted at the appropriate line of the video stream
according to RP 165. The start pixel position of the inserted packet will be based on the
SAV position of that line such that the last byte of the EDH packet (the checksum) will be
placed in the sample immediately preceding the start of the SAV TRS word.
Note 2:
It is also the responsibility of the user to ensure that there is sufficient space in
the horizontal blanking interval for the EDH packet to be inserted.
CRC Update of Existing Packets
When the EDH_CRC_UPDATE bit is set HIGH, the GS9092A will not generate any new
EDH packets, but will instead update the CRC bytes of the existing EDH packets within
the input video data stream. Incoming EDH flags are preserved and can be read from the
EDH_FLAG register, which becomes read-only (Table 3-8).
When EDH packets are detected, the EDH_FLAG register is updated on each field. These
registers will be cleared LOW if no EDH packet is detected during blanking at the end of
the vertical blanking period (falling edge of V).
H Timing (H_CONFIG = LOW)
3FF
3FF
000
000
000
000
XYZ
SAV
XYZ
EAV
LAST
FF &
AP
PIXEL
FIRST
AP
PIXEL
FIRST
FF
PIXEL
FIRST
AP
PIXEL
FIRST
FF
PIXEL
LAST
FF &
AP
PIXEL
H Timing (H_CONFIG = HIGH)


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