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GS9092A Datasheet(PDF) 36 Page - Semtech Corporation

Part # GS9092A
Description  270Mb/s Serializer for SDI and DVB-ASI
Download  61 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS9092A Datasheet(HTML) 36 Page - Semtech Corporation

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GS9092A GenLINX® III 270Mb/s Serializer for SDI and
DVB-ASI
Final Data Sheet
34715 - 5
February 2013
36 of 61
3.6 Data-Through Mode
The GS9092A may be configured by the application layer to operate as a simple
parallel-to-serial converter. In this mode, the device presents data to the output buffer
without performing any scrambling, encoding, or word-alignment.
Data-through mode is enabled only when both the SMPTE_BYPASS and DVB_ASI pins
are set low by the application layer.
3.7 Additional Processing Functions
The GS9092A contains an additional data processing block which is available in SMPTE
mode only (see SMPTE Mode on page 34).
3.7.1 Input Data Blank
The GS9092A can crop the video input data, where the cropped region is set to blanking
levels. All input video and ancillary data will be set to blanking levels by the device,
however, the TRS will be protected at all times.
When the BLANK pin is set LOW, the input video will be set to blanking levels until the
BLANK pin is re-asserted HIGH. When set HIGH, the input video will not be blanked.
This allows portions of the input video to be dynamically cropped, based on the timing
of the BLANK input.
The BLANK input should be synchronized to the PCLK unless the internal FIFO is
enabled and configured for video mode. If the FIFO is in video mode, the BLANK input
should not be used.
3.7.2 Automatic Video Standard Detection
The GS9092A can detect the input video standard by using the timing parameters
extracted from the received TRS ID words or supplied H, V, and F timing signals.
Total samples per line, active samples per line, total lines per field/frame and active lines
per field/frame are calculated and presented to the host interface via the four
RASTER_STRUCTURE registers (Table 3-3).
In addition to the RASTER_STRUCTURE registers, bit 4 of the VIDEO_STANDARD
register contains a status bit, STD_LOCK, which will be set HIGH whenever the device
has achieved full synchronization to the detected video standard.
The STD_LOCK bit, as well as the RASTER_STRUCTURE registers will default to zero
under any of the following conditions:
• RESET is LOW
• SMPTE_BYPASS is LOW
Note:
When the video data is removed, but the PCLK remains, the VIDEO_STANDARD
register will contain the last detected standard. To clear the registers, the PCLK must be
removed as well or the device must be reset.


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