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GS2970A Datasheet(PDF) 31 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 31 Page - Semtech Corporation |
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31 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 31 of 150 The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked (LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’. NOTE: the serial digital output is muted when the GS2970A is unlocked. 4.5 Serial Digital Reclocker The GS2970A includes both a PLL stage and a sampling stage. The PLL is comprised of two distinct loops: • A coarse frequency acquisition loop sets the centre frequency of the integrated Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock • A fine frequency and phase locked loop aligns the VCO’s phase and frequency to the input serial digital stream The frequency lock loop results in a very fast lock time. The sampling stage re-times the serial digital input with the locked VCO clock. This generates a clean serial digital stream, which may be output on the SDO/SDO output pins and converted to parallel data for further processing. Parallel data is not affected by RC_BYP. Only the SDO is affected by this pin. 4.5.1 PLL Loop Bandwidth The fine frequency and phase lock loop in the GS2970A reclocker is non-linear. The PLL loop bandwidth scales with the jitter amplitude of the input data stream; automatically reduces bandwidth in response to higher jitter. This allows the PLL to reject more of the jitter in the input data stream and produce a very clean reclocked output. The loop bandwidth of the GS2970A PLL is defined with 0.2UI input jitter. The bandwidth is controlled by the LB_CONT pin. Under nominal conditions, with the LB_CONT pin floating and 0.2UI input jitter applied, the loop bandwidth is set to 1/1000 of the frequency of the input data stream. Connecting the LB_CONT pin to 3.3V reduces the bandwidth to half of the nominal setting. Connecting the LB_CONT pin to GND increases the bandwidth to double the nominal setting. Table 4-2 below summarizes this information. Table 4-1:Serial Digital Output SDO_EN/DIS RC_BYP SDO/SDO 0X Disabled 11 Re-timed 10 Buffered (not re-timed) |
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