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GS2970A Datasheet(PDF) 30 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 30 Page - Semtech Corporation |
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30 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 30 of 150 4.2.2 Level B Mapping The 2 x 292 HD SDI interface - this can be two distinct links running at 1.5Gb/s or one 3Gb/s link formatted according to SMPTE 292 on two 10-bit links (Y/C interleaved). For 1080p/50/59.94/60 4:2:2 video formats, each link should be line-interleaved as per SMPTE 372M. See Figure 4-2: Figure 4-2:Level B Mapping The GS2970A distinguishes between Level A and Level B mappings at 3Gb/s. When Level B data is detected, each 10-bit link is demultiplexed into its individual component streams, and most video processing features, including error detection and correction are enabled separately for Data Stream 1 and Data Stream 2 (Link A and Link B, respectively). Note that audio demultiplexing and ancillary data extraction can only be enabled for one link for 3Gb/s Level B data. Data Stream 1 or Data Stream 2 can be selected via the host interface. 4.3 Serial Digital Input The GS2970A can accept serial digital inputs compliant with SMPTE 424M, SMPTE 292 and SMPTE 259M-C. The serial digital input buffer features 50 Ω input termination and can be DC-coupled to Semtech's 3Gb/s-capable equalizers. 4.4 Serial Digital Loop-Through Output The GS2970A contains a 100 Ω differential serial output buffer which can be configured to output either a retimed or a buffered version of the serial digital input. The SDO and SDO outputs of this buffer can interface directly to a 3Gb/s-capable, SMPTE compliant Gennum cable driver. See 5.1 Typical Application Circuit on page 145. When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the serial input. When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version of the serial input, bypassing the internal reclocker. The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both SDO and SDO pins are set to VDD and remain static. Data Stream 1 (”Link A”) Data Stream 2 (”Link 2”) EAV HANC SAV Active Video “double” TRS headers from interleaved HD-SDI; multiplexed Y/C data |
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