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GS2970A Datasheet(PDF) 14 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 14 Page - Semtech Corporation |
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14 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 14 of 150 G7 SMPTE_BYPASS Input/Output CONTROL SIGNAL INPUT/OUTPUT Please refer to the Input/Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Indicates the presence of valid SMPTE data. When the AUTO/MAN bit in the host interface register is HIGH (Default), this pin is an OUTPUT. SMPTE_BYPASS is HIGH when the device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW under all other conditions. When the AUTO/MAN bit in the host interface register is LOW, this pin is an INPUT: No SMPTE scrambling takes place, and none of the I/O processing features of the device are available when SMPTE_BYPASS is set LOW. When SMPTE_BYPASS is set HIGH, the device carries out SMPTE scrambling and I/O processing. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. G8DVB_ASI Input/Output CONTROL SIGNAL INPUT Please refer to the Input/Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable/disable DVB-ASI data extraction in manual mode. When the AUTO/MAN bit in the host interface is LOW, this pin is an input and when the DVB_ASI pin is set HIGH the device will carry out DVB_ASI data extraction and processing. The SMPTE_BYPASS pin must be set LOW. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. When the AUTO/MAN bit in the host interface is HIGH (default), DVB-ASI is configured as a status output (set LOW), and DVB-ASI input streams are not supported or recognized. H1 BUFF_VDD Input Power POWER pin for the serial digital output 50 Ω buffer. Connect to 3.3V DC analog. H2 BUFF_GND Input Power GND pin for the cable driver buffer. Connect to analog GND. H3 AUDIO_EN/DIS Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Enables or disables audio extraction. H4 WCLK Output 48kHz word clock for Audio. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. H5 TIM_861 Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select CEA-861 timing mode. When TIM_861 is HIGH, the device outputs CEA 861 timing signals (HSYNC/VSYNC/DE) instead of H:V:F digital timing signals. H6 XTAL_OUT Digital Output Buffered 27MHz crystal output. Can be used to cascade the crystal signal. Table 1-1:Pin Descriptions (Continued) Pin Number Name Timing Type Description |
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