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GS2970A Datasheet(PDF) 65 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 65 Page - Semtech Corporation |
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65 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 65 of 150 Separate SD_AUDIO_ERROR_MASK and HD_AUDIO_ERROR_MASK registers for SD and HD audio cores are also provided, allowing select error conditions to be reported. Each bit of each ERROR_MASK register corresponds to a unique error type. By default (at power up or after system reset), all bits of the ERROR_MASK registers are zero, enabling all errors to be reported. Individual error detection may be disabled by setting the corresponding bit HIGH in the mask registers. Error conditions are indicated by a VIDEO _ERROR signal and an AUDIO_ERROR signal, which are available for output on the multifunction I/O output pins. The two signals are also combined into a summary DATA_ERROR signal, which is also available on the multifunction I/O pins. These signals are normally HIGH, but are set LOW by the device when an error condition has been detected. These signals are a logical 'NOR' of the appropriate error status flags stored in the ERROR_STAT_X register, which are gated by the bit settings in the ERROR_MASK registers. When an error status bit is HIGH and the corresponding error mask bit is LOW, the corresponding DATA_ERROR signal is set LOW by the device. The ERROR_STAT_X registers, and correspondingly the DATA_ERROR, VIDEO_ERROR, and AUDIO_ERROR signals, are cleared at the start of the next video field or when read via the host interface, which ever condition occurs first. Note that any AUDIO_ERROR condition will cause DATA_ERROR to assert. Use the SD_AUDIO_ERROR_MASK and HD_AUDIO_ERROR_MASK registers if masking these events is desired. All bits of the ERROR_STAT_X registers are also cleared under any of the following conditions: 1. LOCKED signal = LOW. 2. SMPTE_BYPASS = LOW. 3. When a change in video standard has been detected. 4. RESET_TRST = LOW Table 4-13 shows the ERROR_STAT_X register and ERROR_MASK_X register. NOTE: Since the error indication registers are cleared once per field, if an external host micro is polling the error registers periodically, an error flag may be missed if it is intermittent, and the polling frequency is less than the field rate. Table 4-13:Error Status Register and Error Mask Register Video Error Status Register Video Error Mask Register SAV_ERR (02h, 03h) SAV_ERR_MASK (037h, 038h) EAV_ERR (02h, 03h) EAV_ERR_MASK (037h, 038h) YCRC_ERR (02h, 03h) YCRC_ERR_MASK (037h, 038h) CCRC_ERR (02h, 03h) CCRC_ERR_MASK (037h, 038h) LNUM_ERR (02h, 03h) LNUM_ERR_MASK (037h, 038h) YCS_ERR (02h, 03h) YCS_ERR_MASK (037h, 038h) CCS_ERR (02h, 03h) CCS_ERR_MASK (037h, 038h) AP_CRC_ERR (02h) AP_CRC_ERR_MASK (037h) |
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