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GS2970A Datasheet(PDF) 62 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 62 Page - Semtech Corporation |
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62 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 62 of 150 By default (after power up or after systems reset), the four RASTER_STRUCTURE, VD_STD, STD_LOCK and INT/PROG registers are set to zero. These registers are also cleared when the SMPTE_BYPASS pin is LOW. 4.13.1 2K Support In order to fully support 2K standards without customer intervention, Semtech provides FPGA code for enhancing the GS2970A's 2K capability. The features of the 2K FPGA enhancement are: • Automatic video standard detection for 2K standards • 1/1.001 rate detection for 2K standards • CEA-861 timing generation for 2K standards • Automatic enabling of audio extraction This enhancement is an interface between the GS2970A and the customer system. The behaviour of the GS2970A with or without the additional 2K enhancement FPGA code is identical from a user-perspective. Figure 4-29:2K Feature Enhancement 4.14 Data Format Detection & Indication In addition to detecting the video standard, the GS2970A detects the data format, i.e. SDTI, SDI, TDM data (SMPTE 346M), etc. This information is represented by bits in the DATA_FORMAT_DSX register accessible through the host interface. Data format detection is only carried out when the LOCKED signal is HIGH. GS2970A Host Interface Control PLL ÷2 ÷1 GIb_MUX 0 1 GIb_Buf Level_B FPGA Level_B Vid_Out[19:0] HVF[2:0] WO_2K STAT3 STAT4 STAT5 GS2970A_GSPI_SDI GS2970A_GSPI_CS GS2970A_GSPI_SCLK GS2970A_GSPI_SDOUT reset Host_GSPI_CS Host_GSPI_SCLK Host_GSPI_SDI Host_GSPI_SDOUT Pclk Pclk_div2 smpte_bypass_i tim_861 clk_27M_ref dy_in_i[9:0] dc_in_i[9:0] fvh_o[2:0] Host_GSPI_busy Level_B rate_m_o std_2K_det_o dy_out_o[9:0] dc_out_o[9:0] fvh_i[2:0] |
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