GS2970A datasheet(42/150 Pages) SEMTECH

Part #	GS2970A

Description	3Gb/s, HD, SD SDI Receiver Complete with SMPTE Audio and Video Processing

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Manufacturer	SEMTECH [Semtech Corporation]

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42 / 150 page

GS2970A 3Gb/s, HD, SD SDI Receiver

Data Sheet

54244 - 2

September 2012

42 of 150

Figure 4-8:DDR Video Interface - 3G Level B

The GS2970A has the ability to shift the Setup/Hold window on the receive interface, by

using an on-chip delay line to shift the phase of PCLK with respect to the data bus.

The timing of the PCLK output, relative to the data, can be adjusted through the host

interface registers. Address 06Ch contains the delay line controls:

Bit[5] (DEL_LINE_CLK_SEL) is a coarse delay adjustment that selects between the

default (nominal) PCLK phase and a quadrature phase, for a 90º phase shift.

Bits[4:0] (DEL_LINE_OFFSET) comprise a fine delay adjustment to shift the PCLK in

40ps increments (typical conditions). The maximum fine delay adjustment is

approximately 1.2ns under nominal conditions.

An example delay adjustment over min/typ/max conditions is illustrated in Figure 4-9.

The target delay is 0.84ns under typical conditions (approximately 45º PCLK phase

shift), and requires a control word setting of 0x0014 for address 0x006C.

DOUT0[9:0]

DOUT1[9:0]

Data Stream 1

Data Stream 2

20-bit bus

(transition rate = 74.25MHz)

PCLK

(148.5MHz)

10-bit bus

(transition rate = 148.5MHz)

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