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GS2970A Datasheet(PDF) 41 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 41 Page - Semtech Corporation |
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41 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 41 of 150 4.9.6 DDR Parallel Clock Timing The GS2970A has the ability to transmit 10-bit parallel video data with a DDR (Dual Data Rate) pixel clock over a single-ended interface. DDR Mode can be enabled when the SDI data bandwidth is 3Gb/s. In this case, the 10-bit parallel data rate is 297Mb/s, and the frequency of the DDR clock is 148.5MHz (10-bit output in 3G mode). The DDR pixel clock avoids the need to operate a high-drive pixel clock at 297MHz. This reduces power consumption, clock drive strength, and noise generation, and precludes from generating excessive EMI had PCLK on the board have to run at 297MHz. It also enables easier board routing and avoids the need to use the higher-speed I/Os on FPGAs, which may require more expensive speed grades. Figure 4-7 and Figure 4-8 show how the DDR interface operates. The pixel clock is transmitted at half the data rate, and the interleaved data is sampled at the receiver on both clock edges. Figure 4-7:DDR Video Interface - 3G Level A 10-bit data output SD format LOW HIGH X LOW LOW 27MHz 10-bit ASI output SD format LOW HIGHX LOW HIGH 27MHz Table 4-6:GS2970A PCLK Output Rates (Continued) Output Data Format Pin/Control Bit Settings PCLK Rate 20bit/ 10bit RATE_DET0 RATE_DET1 SMPTE_ BYPASS DVB-ASI Y2 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Y3 Y4 Y5 Y6 Y7 Y8 Y9 20-bit bus (transition rate = 74.25MHz) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Cb 0 Cb 1 Cb 2 Cb 3 Cb 4 Cr 0 Cr 1 Cr 2 Cr 3 Cr 4 PCLK (148.5MHz) Y0 Cb0 Y1 Cr0 10-bit bus (transition rate = 148.5MHz) |
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