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GS2970A Datasheet(PDF) 35 Page - Semtech Corporation |
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GS2970A Datasheet(HTML) 35 Page - Semtech Corporation |
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35 / 150 page  GS2970A 3Gb/s, HD, SD SDI Receiver Data Sheet 54244 - 2 September 2012 35 of 150 4.7.2 Signal Interruption The device tolerates a signal interruption of up to 10 μs without unlocking, as long as no TRS words are deleted by this interruption. If a signal interruption of greater than 10 μs is detected, the lock detection algorithm may lose the current data rate, and LOCKED will de-assert until the data rate is re-acquired by the lock detection block. 4.8 SMPTE Functionality 4.8.1 Descrambling and Word Alignment The GS2970A performs NRZI to NRZ decoding and data descrambling according to SMPTE 424M/SMPTE 292/SMPTE 259M-C and word aligns the data to TRS sync words. When operating in manual mode (AUTO/MAN = LOW), the device only carries out SMPTE decoding, descrambling and word alignment when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW. When operating in Auto mode (AUTO/MAN = HIGH), the GS2970A carries out descrambling and word alignment to enable the detection of TRS sync words. When two consecutive valid TRS words (SAV and EAV), with the same bit alignment have been detected, the device word-aligns the data to the TRS ID words. TRS ID word detection is a continuous process. The device remains in SMPTE mode until TRS ID words fail to be detected. NOTE 1: Both 8-bit and 10-bit TRS headers are identified by the device. NOTE 2: In 3G Level B mode, the device only supports Data Stream 1 and Data Stream 2 having the same bit width (i.e. both data streams contain 8-bit data, or both data streams contain 10-bit data). If the bit widths between the two data streams are different, the GS2970A cannot word align the input stream, and switches in Data-Through mode. 4.9 Parallel Data Outputs The parallel data outputs are aligned to the rising edge of the PCLK. 4.9.1 Parallel Data Bus Buffers The parallel data bus, status signal outputs and control signal input pins are all connected to high-impedance buffers. The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and IO_GND pins. All output buffers (including the PCLK output), are set to high-impedance in Reset mode (RESET_TRST = LOW). |
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