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GS1661A Datasheet(PDF) 2 Page - Semtech Corporation |
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GS1661A Datasheet(HTML) 2 Page - Semtech Corporation |
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2 / 85 page  GS1661A HD/SD SDI Receiver Data Sheet 54387 - 2 September 2012 2 of 85 Parallel data outputs are provided in 20-bit or 10-bit format for HD and SD video rates, with a variety of mapping options. As such, this parallel bus can interface directly with video processor ICs, and output data can be multiplexed onto 10 bits for a low-pin count interface. Functional Block Diagram GS1661A Functional Block Diagram Buffer Mux Reclocker with Integrated VCO SDI SDO SDO Serial to Parallel Converter Descramble, Word Align, Rate Detect Flywheel Video Standard Detect TRS Detect Timing Extraction Mux DVB-ASI Decoder Illegal code remap, TRS/ Line Number/ CRS Insertion, EDH Packet Insertion ANC/ Checksum /352M Extraction GSPI and JTAG Controller Host Interface Output Mux/ Demux Crystal Buffer/ Oscillator LF LB_CONT VBG I/O Control Buffer SDI NGEN EQ AGC+ AGC- DOUT[19:0] PCLK LOCKED |
Similar Part No. - GS1661A |
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Similar Description - GS1661A |
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