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GS1661A Datasheet(PDF) 53 Page - Semtech Corporation |
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GS1661A Datasheet(HTML) 53 Page - Semtech Corporation |
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53 / 85 page  GS1661A HD/SD SDI Receiver Data Sheet 54387 - 2 September 2012 53 of 85 2. SMPTE_BYPASS = LOW. 3. When a change in video standard has been detected. 4. RESET_TRST = LOW Table 4-13 shows the ERROR_STAT_X register and ERROR_MASK_X register. NOTE: Since the error indication registers are cleared once per field, if an external host micro is polling the error registers periodically, an error flag may be missed if it is intermittent, and the polling frequency is less than the field rate. 4.15.1 TRS Error Detection TRS error flags are generated by the GS1661A under the following two conditions: 1. A phase shift in received TRS timing is observed on a non-switching line. 2. The received TRS Hamming codes are incorrect. Both SAV and EAV TRS words are checked for timing and data integrity errors. For HD mode, only the Y channel TRS codes are checked for errors. Both 8-bit and 10-bit TRS code words are checked for errors. The SAV_ERR bit of the ERROR_STAT_X register is set HIGH when an SAV TRS error is detected. The EAV_ERR bit of the ERROR_STAT_X register is set HIGH when an EAV TRS error is detected. 4.15.2 Line Based CRC Error Detection The GS1661A calculates line based CRCs for HD video signals. CRC calculations are done for each 10-bit channel (Y and C for HD video). These calculated CRC values are compared with the received CRC values. Table 4-13: Error Status Register and Error Mask Register Video Error Status Register Video Error Mask Register SAV_ERR (02h, 03h) SAV_ERR_MASK (037h, 038h) EAV_ERR (02h, 03h) EAV_ERR_MASK (037h, 038h) YCRC_ERR (02h, 03h) YCRC_ERR_MASK (037h, 038h) CCRC_ERR (02h, 03h) CCRC_ERR_MASK (037h, 038h) LNUM_ERR (02h, 03h) LNUM_ERR_MASK (037h, 038h) YCS_ERR (02h, 03h) YCS_ERR_MASK (037h, 038h) CCS_ERR (02h, 03h) CCS_ERR_MASK (037h, 038h) AP_CRC_ERR (02h) AP_CRC_ERR_MASK (037h) FF_CRC_ERR (02h) FF_CRC_ERR_MASK (037h) VD_STD_ERR (02h, 03h) VD_STD_ERR_MASK (037h) |
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