SCL

SDA

S

S

P

P

22

INA3221-Q1

SBOS776B – MARCH 2016 – REVISED MARCH 2016

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Copyright © 2016, Texas Instruments Incorporated

(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not production tested.

A0 = A1 = 0.

Figure 31. Bus Timing

PARAMETER

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

SCL operating frequency

0.001

0.4

0.001

2.44

MHz

Bus free time between stop and start conditions

1300

160

ns

Hold time after repeated START condition.

After this period, the first clock is generated.

600

160

ns

Repeated start condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

0

0

ns

Data valid time

1200

260

ns

Data setup time

100

10

ns

SCL clock low period

1300

270

ns

SCL clock high period

600

60

ns

Data fall time

500

150

ns

Clock fall time

300

40

ns

Clock rise time

300

40

ns

Clock rise time for SCLK

≤ 100 kHz

1000

ns

8.5.3 SMBus Alert Response

The INA3221-Q1 responds to the SMBus alert response address. The SMBus alert response provides a quick

fault identification for simple slave devices. When an alert occurs, the master broadcasts the alert response slave

address (0001 100) with the R/W bit set high. Following this alert response, any slave devices that generated an

alert identify themselves by acknowledging the alert response, and sending their respective address on the bus.

more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an

acknowledge, and continues to hold the alert line low until the interrupt is cleared.