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INA3221-Q1 Datasheet(PDF) 14 Page - Texas Instruments

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Part # INA3221-Q1
Description  Current and Voltage Monitor with Programmable Overcurrent Alerts
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA3221-Q1 Datasheet(HTML) 14 Page - Texas Instruments

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INA3221-Q1
SBOS776B – MARCH 2016 – REVISED MARCH 2016
www.ti.com
Product Folder Links: INA3221-Q1
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Copyright © 2016, Texas Instruments Incorporated
Feature Description (continued)
The timing control alert function is only monitored at power-up or when a software reset is issued by setting the
reset bit (RST, bit 15) in the Configuration register. The timing control alert function timing is based on the default
device settings at power-up. Writing to the Configuration register before the timing control alert function
completes the full sequence results in disabling the timing control alert until power is cycled or a software reset is
issued.
8.3.2.5 Default Settings
The default register power-up states are listed in the Register Maps section. These registers are volatile; if
programmed to a value other than the default values shown in Table 3, the registers must be reprogrammed
every time the device powers up.
8.3.3 Software Reset
The INA3321 features a software reset that reinitializes the device and register settings to default power-up
values without having to cycle power to the device. Use bit 15 (RST) of the Configuration register to perform a
software reset. Setting RST reinitializes all registers and settings to the default power state with the exception of
the power-valid output state.
If a software reset is issued, the INA3221-Q1 holds the output of the PV pin until the power-valid detection
sequence completes. The Power-Valid Upper Limit and Power-Valid Lower limit registers return to the default
state when the software reset has been issued. Therefore, any reprogrammed limit registers are reset, resulting
in the original power-valid thresholds validating the power-valid conditions. This architecture prevents interruption
to circuitry connected to the power valid output during a software reset event.


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