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INA3221-Q1 Datasheet(PDF) 11 Page - Texas Instruments

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Part # INA3221-Q1
Description  Current and Voltage Monitor with Programmable Overcurrent Alerts
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA3221-Q1 Datasheet(HTML) 11 Page - Texas Instruments

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INA3221-Q1
www.ti.com
SBOS776B – MARCH 2016 – REVISED MARCH 2016
Product Folder Links: INA3221-Q1
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Copyright © 2016, Texas Instruments Incorporated
Feature Description (continued)
8.3.2 Alert Monitoring
The INA3221-Q1 allows programmable thresholds that make sure the intended application operates within the
desired operating conditions. Multiple monitoring functions are available using four alert pins: Critical, Warning,
PV (power valid), and TC (timing control). These alert pins are open-drain connections.
8.3.2.1 Critical Alert
The critical-alert feature monitors functions based on individual conversions of each shunt-voltage channel. The
critical-alert limit feature compares the shunt-voltage conversion for each shunt-voltage channel to the value
programmed into the corresponding limit register, in order to determine if the measured value exceeds the
intended limit. Exceeding the programmed limit indicates that the current through the shunt resistor is too high.
At power-up, the default critical-alert limit value for each channel is set to the positive full-scale value, effectively
disabling the alert. Program the corresponding limit registers at any time to begin monitoring for out-of-range
conditions. The Critical alert pin pulls low if any channel measurement exceeds the limit present in the
corresponding-channel critical-alert limit register. When the Critical alert pulls low, read the Mask/Enable register
to determine which channel caused the critical alert flag indicator bit (CF1-3) to assert (= 1).
8.3.2.1.1
Summation Control Function
The INA3221-Q1 also allows the Critical alert pin to be controlled by the summation control function. This
function adds the single shunt-voltage conversions for the desired channels (set by SCC1-3 in the Mask/Enable
register) in order to compare the combined sum to the programmed limit.
The SCC bits either disable the summation control function or allow the summation control function to switch
between including two or three channels in the Shunt-Voltage Sum register. The Shunt-Voltage Sum Limit
register contains the programmed value that is compared to the value in the Shunt-Voltage Sum register in order
to determine if the total summed limit is exceeded. If the shunt-voltage sum limit value is exceeded, the Critical
alert pin pulls low. Either the summation alert flag indicator bit (SF) or the individual critical alert limit bits (CF1-3)
in the Mask/Enable register determine the source of the alert when the Critical alert pin pulls low.
For the summation limit to have a meaningful value, use the same shunt-resistor value on all included channels.
Unless equal shunt-resistor values are used for each channel, do not use this function to add the individual
conversion values directly together in the Shunt-Voltage Sum register to report the total current.
8.3.2.2 Warning Alert
The warning alert monitors the averaged value of each shunt-voltage channel. The averaged value of each
shunt-voltage channel is based on the number of averages set with the averaging mode bits (AVG1-3) in the
Configuration register. The average value updates in the shunt-voltage output register each time there is a
conversion on the corresponding channel. The device compares the averaged value to the value programmed in
the corresponding-channel Warning Alert Limit register to determine if the averaged value has been exceeded,
indicating whether the average current is too high. At power-up, the default warning-alert limit value for each
channel is set to the positive full-scale value, effectively disabling the alert. The corresponding limit registers can
be programmed at any time to begin monitoring for out-of-range conditions. The Warning alert pin pulls low if any
channel measurements exceed the limit present in the corresponding-channel Warning Alert Limit register. When
the Warning alert pin pulls low, read the Mask/Enable register in order to determine which channel warning alert
flag indicator bit (WF1-3) is asserted (= 1).


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