5

INA3221-Q1

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SBOS776B – MARCH 2016 – REVISED MARCH 2016

Product Folder Links: INA3221-Q1

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Copyright © 2016, Texas Instruments Incorporated

(1)

RTI = Referred-to-input.

(2)

Input leakage is positive (current flows into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur

under different input conditions.

(3)

SMBus timeouts in the INA3221-Q1 reset the interface whenever SCL is low for more than 28 ms.

7.5 Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

Shunt voltage input

–163.84

163.8

mV

Bus voltage input

0

26

V

CMR

Common-mode rejection

110

120

dB

±40

±80

μV

0.1

0.5

μV/°C

PSRR

15

μV/V

±8

±16

mV

80

μV/°C

PSRR

vs power supply

0.5

mV/V

Input bias current at IN+

10

μA

Input bias current at IN–

10 || 670

μA || kΩ

(IN+ pin) + (IN– pin), power-down mode

0.1

0.5

μA

DC ACCURACY

ADC native resolution

13

Bits

1-LSB step size

Shunt voltage

40

μV

Bus voltage

8

mV

Shunt voltage gain error

0.1%

0.25%

10

50

ppm/°C

Bus voltage gain error

0.1%

0.25%

10

50

ppm/°C

DNL

Differential nonlinearity

±0.1

LSB

ADC conversion time

CT bit = 000

140

154

µs

CT bit = 001

204

224

CT bit = 010

332

365

CT bit = 011

588

646

CT bit = 100

1.1

1.21

ms

CT bit = 101

2.116

2.328

CT bit = 110

4.156

4.572

CT bit = 111

8.244

9.068

SMBus

28

35

ms

DIGITAL INPUT/OUTPUT

Input capacitance

3

pF

Leakage input current

0 V

0.1

1

μA

High-level input voltage

6

V

Low-level input voltage

–0.5

V

Low-level output

voltage

SDA, critical, warning, PV

0

0.4

V

TC

0

0.4

Hysteresis voltage

500

mV

POWER SUPPLY

Quiescent current

350

450

μA

Power-down mode

0.5

2

Power-on reset threshold

2

V