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INA3221-Q1 Datasheet(PDF) 32 Page - Texas Instruments |
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INA3221-Q1 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 45 page  32 INA3221-Q1 SBOS776B – MARCH 2016 – REVISED MARCH 2016 www.ti.com Product Folder Links: INA3221-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h] This register selects which function is enabled to control the Critical alert and Warning alert pins, and how each warning alert responds to the corresponding channel. Read the Mask/Enable register to clear any flag results present. Writing to this register does not clear the flag bit status. To make sure that there is no uncertainty in the warning function setting that resulted in a flag bit being set, the Mask/Enable register should be read from to clear the flag bit status before changing the warning function setting. Figure 47. Mask/Enable Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — SCC1 SCC2 SCC3 WEN CEN CF1 CF2 CF3 SF WF1 WF2 WF3 PVF TCF CVRF RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20. Mask/Enable Register Field Descriptions Bit Field Type Reset Description 15 Reserved R/W 0h Reserved 14-12 SCC1-3 R/W 0h Summation channel control. These bits determine which shunt voltage measurement channels are enabled to fill the Shunt-Voltage Sum register. The selection of these bits does not impact the individual channel enable or disable status, or the corresponding channel measurements. The corresponding bit is used to select if the channel is used to fill the Shunt-Voltage Sum register. 0 = Disabled (default) 1 = Enabled 11 WEN R/W 0h Warning alert latch enable. These bits configure the latching feature of the Warning alert pin. 0 = Transparent (default) 1 = Latch enabled 10 CEN R/W 0h Critical alert latch enable. These bits configure the latching feature of the Critical alert pin. 0 = Transparent (default) 1 = Latch enabled 9-7 CF1-3 R/W 0h Critical-alert flag indicator. These bits are asserted if the corresponding channel measurement has exceeded the critical alert limit resulting in the Critical alert pin being asserted. Read these bits to determine which channel caused the critical alert. The critical alert flag bits are cleared when the Mask/Enable register is read back. 6 SF R/W 0h Summation-alert flag indicator. This bit is asserted if the Shunt Voltage Sum register exceeds the Shunt Voltage Sum Limit register. If the summation alert flag is asserted, the Critical alert pin is also asserted. The Summation Alert Flag bit is cleared when the Mask/Enable register is read back. 5-3 WF1-3 R/W 0h Warning-alert flag indicator. These bits are asserted if the corresponding channel averaged measurement has exceeded the warning alert limit, resulting in the Warning alert pin being asserted. Read these bits to determine which channel caused the warning alert. The Warning Alert Flag bits clear when the Mask/Enable register is read back. 2 PVF R/W 0h Power-valid-alert flag indicator. This bit can be used to be able to determine if the power valid (PV) alert pin has been asserted through software rather than hardware. The bit setting corresponds to the status of the PV pin. This bit does not clear until the condition that caused the alert is removed, and the PV pin has cleared. 1 TCF R/W 11h Timing-control-alert flag indicator. Use this bit to determine if the timing control (TC) alert pin has been asserted through software rather than hardware. The bit setting corresponds to the status of the TC pin. This bit does not clear after it has been asserted unless the power is recycled or a software reset is issued. The default state for the timing control alert flag is high. 0 CVRF R/W 0h Conversion-ready flag. Although the INA3221-Q1 can be read at any time, and the data from the last conversion are available, the conversion ready bit is provided to help coordinate single-shot conversions. The conversion bit is set after all conversions are complete. Conversion ready clears under the following conditions: 1. Writing the Configuration register (except for power-down or disable-mode selections). 2. Reading the Mask/Enable register. |
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