1

9

1

0

0

0

0

0

A0

Frame 1: SMBus ALERT Response Address Byte

Frame 2: Slave Address Byte

(1)

Start By

Master

ACK By

Device

Stop By

Master

No ACK By

Master

From

Device

1

1

0

0

0

0

R/W

SCL

SDA

1

0

9

0

1

1

1

9

9

9

1

0

0

0

0

0

A0

R/W

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1: Two-Wire Slave Address Byte

(1)

Frame 2: Data MSByte

(2)

Frame 3: Data LSByte

(2)

Start By

Master

ACK By

Device

ACK By

Master

Stop By

Master

No ACK By

Master

(3)

SCL

SDA

From

Device

From

Device

21

INA3221-Q1

www.ti.com

SBOS776B – MARCH 2016 – REVISED MARCH 2016

Product Folder Links: INA3221-Q1

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Copyright © 2016, Texas Instruments Incorporated

(1)

The value of the slave address byte is determined by the A0 pin setting; see Table 1.

(2)

Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated.

See Figure 27.

(3)

The master can also send an ACK.

Figure 29. Timing Diagram for Read Word Format

Figure 30 shows the timing diagram for the SMBus Alert response operation.

(1)

The value of the Slave Address Byte is determined by the A0 pin setting; see Table 1.

Figure 30. Timing Diagram for SMBus Alert

When the bus is idle, the SDA and SCL lines are pulled high by the pull-up resistors. The master generates a

start condition followed by a valid serial byte with the high-speed (Hs) master code 00001XXX. This transmission

is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA3221-Q1 does not

acknowledge the Hs master code, but does recognize it and switches its internal filters to support 2.44-MHz

operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission

speeds up to 2.44 MHz are allowed. Instead of using a stop condition, the master uses a repeated start

conditions to secure the bus in Hs mode. A stop condition ends the Hs mode, and switches all internal INA3221-

Q1 filters to support F/S mode.

Figure 31 shows the bus timing, and Table 2 lists the bus timing definitions.