16

IDT77V106L25

Jitter at 25.6Mbps at point 4 with respect to point 1

Jitter at 25.6Mbps at point 5 with respect to point 1

Jitter at 51.2Mbps at point 4 with respect to point 1

Jitter at 51.2Mbps at point 5 with respect to point 1

From the above measurements taken, the amount of jitter being added at each TX point is not significant. These tests were also run for extended periods

of time (64 hours) and no bit error were seen.

Line Side (Serial) Interface

PHY to Magnetics Interface

A standard connection to 100

Ω and120Ω unshieldedtwistedpaircablingisshowninFigure16.Notethatthetransmitsignalissomewhatattenuated

in order to meet the launch amplitude specified by the standards. The external receive circuitry is designed to attenuate low frequencies in order to

compensate for the high frequency attenuation of the cable.

Also, the receive circuitry biases the positive and negative RX inputs to slightly different voltages. This is done so that the receiver does not receive false

signals in the absence of a real signal. This can be important because the 77V106L25 does not disable error detection or interrupts when an input signal

is not present.

When connecting to UTP at 51.2 Mbps, it is necessary to use magnetics with sufficient bandwidth. Refer to Table 4 for the recommended magnetics.