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IDT77V106L25 Datasheet(PDF) 15 Page - Integrated Device Technology |
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IDT77V106L25 Datasheet(HTML) 15 Page - Integrated Device Technology |
15 / 27 page ![]() 15 IDT77V106L25 Da ta Da ta Da ta Data Da ta Data SW ITCH Lo op Tim ing M od e L oop Tim ing M od e Loo p Timing Mode Line Car d 2 Line Car d 3 Line Ca rd 4 CLK CLK CL K RX RX RX TX TX TX TX RX No rm al M ode Line Ca rd 1 OS C 1 2 3 4 5 Figure 15 Figure 15. Test Setup for Loop Timing Jitter Measurements Loop Timing Jitter Specification Line Rate Data Rate Min. Typ. Max. Note Mbps Mbps 32 25.6 — 100 ps — Using 32Mhz OSC 64 51.2 — 100 ps — Using 64Mhz OSC The waveforms below show some of the measurements taken with the set-up in Figure 15. Using the formula above, the jitter specification was derived. For example, at data rate 25.63 Mbps, jitter added going through Line Card 3 is 1.5ns - 1.4ns (as shown in the waveform below). TABLE 2 — LOOP TIMING JITTER |
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