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IDT77V106L25

that these counters will be polled from time to time (user selectable) to evaluate performance.

•

Symbol Error Counters

— 8 bits

— counts all invalid 5-bit symbols received

•

Transmit Cell Counters

— 16 bits

— counts all transmitted cells

•

Receive Cell Counters

— 16 bits

— counts all received cells, excluding idle cells and HEC errored cells

•

Receive HEC Error Counters

— 5 bits

— counts all HEC errors received

The TxCell and RxCell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. The Symbol

Error counter and HEC Error counter were given sufficient size to indicate exact counts for low error-rate conditions. If these counters overflow, a gross

condition is occurring, where additional counter resolution does not provide additional diagnostic benefit.

Reading Counters

1. Decide which counter value is desired. Write to the Counter Select Register to the bit location corresponding to the desired counter. This loads

the High and Low Byte Counter Registers with the selected counter’s value, and resets this counter to zero.

Note:Only one counter may be enabled at any time in each of the Counter Select Registers.

2. Read the Counter Registers (low byte and high byte) to get the value.

Further reads may be accomplished in the same manner by writing to the Counter Select Registers.

Note:The PHY takes some time to set up the low and high byte counters after a specific counter has been selected in the Counter Selector

register. This time delay (in µS) varies with the line rate and can be calculated as follows:

Time delay (µS) =

12.5___

line rate (Mbps)

Loop Timing Feature

The 77V106L25 also offers a loop timing feature for specific applications where data needs to be repeated / transmitted using the recovered clock. If

the loop timing mode is enabled in the Enhanced Control Register 1 bit 6, the recovered receive clock is used as to clock out data on transmit side. In

normal mode, the transmitter transmits data using the multiplied oscillator clock.

Jitter in Loop Timing Mode

One of the primary concerns when using loop timing mode is the amount of jitter that gets added each time data is transmitted. Table 2 shows the jitter

measured at various data rates. The set-up shown in Figure 15 was used to perform these tests. The maximum jitter seen was at TX point 5 and the

minimum jitter was at point 2. The loop timing jitter is defined as the amount of jitter generated by each TX node. In other words, the loop timing jitter or the

jitter added by a loop-timed port in the set-up below is the difference between the Total Output Jitter and the Total Input Jitter.